轉職熱搜工作

Design the 5G and next-generation modem processor with cost effective, high speed, and low power hardware performance. This position will develop the modem processor that optimized for modem system. Co-work closely with software and system architecture colleague to analysis the sweet point of system performance and low power. In this position, you will push the physical performance to next level and co-work with place-and-route (PAR) team resolving the bottleneck of speed and power.

1. AI 處理器系統架構/微架構設計 2. AI 處理器系統 BUS 與 memory, power/clock/reset 控制電路及其周邊相關電路設計 3. 車用安全性相關設計

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. Work on 2~4nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

We are looking for a DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality. Key Responsibilities • Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. • Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. • Perform ATPG, fault simulation, and coverage analysis. • Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. • Lead silicon bring-up and debug of test features; conduct failure and yield analysis. • Work with product teams to facilitate pattern generation, validation, and DPPM improvement.

1.AI系統硬體規劃：系統規格與設計需求收集 2.AI系統硬體設計：負責設計和開發硬體系統架構，包括電路設計、元件評估與選擇、客製化元件規劃。 3. AI系統硬體驗證與測試：確認硬體系統正常運作，包含驗證與測試。 4. 跨組織合作：與IC design team、system team、SI/PI team與layout team等等合作，完成系統設計、製作與驗證。 5.客戶與相關廠商支援：包含技術文件撰寫、客戶參考設計支援、on site支援等等。

1. Develop Die-to-die and UCIe digital IP for HPC SOC. 2. Integration of D2D controller and PHY to timing closure and DFT. 3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation. 4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.