轉職熱搜工作

1.Digital design (RTL design, Synthesis, integration, verification) 2.SoC Chip design, integration 3.Familiar with VLSI design flow is a plus

1. Work with design teams to do performance sign off in pre-silicon stage 2. ESL platform and simulation/emulation technology development. 3. Model development (includes behavior modeling/ cycle approximate modeling)

跨團隊合作(如:數位設計,系統應用, 測試, 製程...)以最佳化系統單晶片/平台競爭力及效能 ‧ 基於類比設計技術背景, 與類比設計團隊合作提供混合信號解決方案或IP, 以最佳化系統單晶片/平台競爭力及效能. 於計畫開發過程中, 協調類比團隊共同解決相關問題及克服挑戰, 以達成量產目標

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. Develop scalable platform clocking architecture for automotive SoC 2. Enhance SoC clock architecture and technology development to address the automotive SoC requirements 3. Drive clock architecture and designs to optimize power, performance, and implementation, including physical design and timing closure

MTK電源管理部門設計設計電源管理IC及電源管理單元以滿足各式各樣智慧手機, IOT, 車用, 以及ASIC的需求. 職缺包含: 1. DC-DC 轉換器 2. 線性電壓調節器 3. 切換電壓調節器

1. (內轉佳, 提供發揮舞台, 跨產品線工作流程最佳化) 2. 人格特質: 領導力, 積極正面帶領團隊完成任務 3. 工作範圍:數位SOC設計整合, 包含 - Package, Floorplan, IOMUX, Test-mode design - Clock/CTS/reset/mixed-mode/DFT architecture, design and verification - RTL design and deliver SDC according to IP spec and requirement - SOC/IP DCT/DCG/Fusion synthesis - STA/CDC/CCD/TV/LEC/nLint/CLP tool and task handling

1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution