轉職熱搜工作

- 透過推動跨部門在技術需求、介面定義與交付項目上的一致性，協調先進封裝解決方案的開發（例如 CoWoS、2.5D/3.5D 整合，以及 Chiplet 架構）。 - 主導 SoC Floorplanning 以最佳化 PPA（功耗、效能與晶片面積），並在時序收斂、繞線壅塞、電源域邊界，以及 PDN／熱設計等考量間取得平衡。 - 與封裝團隊合作制定並優化 Ball/Bump 配置（bump/ball map），以滿足 SI/PI、電流承載能力、可製造性與可靠度等需求。

1. 針對各類 benchmark 進行分析，辨識性能瓶頸、功耗瓶頸，並評估熱管理機制之影響。 2. 建置並實作 benchmark 之系統模型，以評估 SoC 最佳化之可行性與潛在效益。 3. 持續追蹤不同平台 benchmark 之最新進展，聚焦於系統層級之改善方向與策略。 4. 彙整分析與建模結果，提出具可落地性之系統/SoC 最佳化建議，並與跨部門團隊協作推進改善與成效驗證。

加入 MediaTek「先進製程平台 DFT」團隊，你的工作直接影響 N4/N3/N2 及更先進世代 Cloud ASIC 的可靠度與良率。 - DFT 架構與插入：針對先進節點 SoC 及 chiplet/3D-IC 設計，定義並實作 Scan（full-scan、compressor）、MBIST、BSD/JTAG 架構；使用 Synopsys / Siemens (Tessent) EDA 工具執行端到端插入流程。 - ATPG 與 Advanced Fault Model：開發並優化 stuck-at、transition delay、cell-aware、path-delay 等 fault model 的 ATPG pattern；驅動 fault coverage closure 並交付 DRC-clean pattern。 - 模擬與驗證：透過 gate-level simulation（VCS/Xcelium）驗證 DFT 邏輯正確性；解決 DFT rule violation 與 coverage gap，確保 tapeout 品質。 - 後矽驗證與測試：主導 CP / FT / HTOL / HVS 各階段 DFT 工作，包含 test mode 驗證、scan chain 連通性測試、MBIST 執行與 repair 確認。 - Volume Diagnosis 與 Yield Ramp：運用 scan/MBIST diagnosis 資料分離系統性缺陷，與製程及 FA 團隊協作加速 yield learning 與技術成熟。 - RMA / DPPM 除錯：利用 DFT diagnosis 流程調查 field return，協助降低 DPPM 並防止 escape。 - 產業前沿：持續追蹤 Cloud ASIC chiplet 測試趨勢、ATE 技術進展與 EDA 新功能，主動將新觀念帶入團隊。 職務要求

解讀客戶的網絡安全需求 從網絡安全需求中推導出功能和安全概念 制定和審查安全系統架構 與 IP 團隊和客戶溝通和協調安全設計 執行系統安全分析（例如：TARA）

Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration. • Document on new flows and processes for AMS Behavioral Modeling. • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc. • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA

• Work with the architecture/micro-architecture/design teams to do white box testing. • Create testplans based on the micro-architecture document with the design team. • Build, maintain and upgrade testbenches and their components using UVM-based methods. • Build custom BFMs for co-sim based module level verification. • Add assertions and checkers to facilitate verification. • Work with the design team to do module level formal verification. • Create controlled random testcases. Pre-debug and provide debug reports. • Check functional coverage and code coverage.

We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team. The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs. The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. • SoC testing architecture design • Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) • Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.

We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 1. Guide customers to complete Signal Integrity and Power Integrity signoff. 2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

We are looking for a highly skilled DFT CAD and Methodology Expert to develop and deploy advanced test methodologies for next-generation data center and AI ASIC. Enhancing the efficiency and quality of our ASIC development and testing procedures. The successful candidate will work within the CAD team to innovate test solutions for complex 2.5D/3DIC, ensuring high quality and yield for advanced packaging technologies. Key Responsibilities • Methodology Development: Develop and deploy robust CAD flows for scan insertion, ATPG, pattern simulation, and Memory BIST (MBIST). • Tool Automation: Create scripts (Python, TCL, Perl) to enhance and automate DFT flows, accelerating simulation runtimes and improving quality of results (QOR). • EDA Tool Integration: Collaborate with EDA vendors to enhance tools for advanced packaging, including test verification and pattern generation. • Support & Debug: Support DFT integration teams with CAD flow issues, debug complex issues, and provide technical mentorship. • 3DIC/2.5D Expertise: Develop and implement testing strategies for chiplets and TSV-based 3D stacks. • Location: Hsinchu, Taipei, Singapore.

• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 • HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。