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  • 國家太空中心-光學酬載組_數位電路設計工程師

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 2~3年工作經驗
    1.研讀、修改與撰寫RTL code (Verilog, VHDL) 2.數位電路設計。 3.承辦及參與委託給業界或學研團隊之研發案。
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  • 【製程設計類】佈局工程師Layout Engineer(ABF Flip Chip/FC-BGA)(桃園廠)

    面議(經常性薪資達4萬元或以上) 40000元 桃園市新屋區 工作經歷不拘
    1.負責 ABF Flip Chip(FC-BGA / FC-CSP)載板 Layout 設計 2.依 IC 封裝規格進行: | Bump / Pad assignment | RDL / Trace routing | Power / Ground 網路規劃 3.與客戶進行技術溝通與問題改善
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  • Digital Design and Automation Engineer

    面議(經常性薪資達4萬元或以上) 40000元 新竹市 工作經歷不拘
    【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=532&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: Front-end to back-end large scale digital circuit design for system-on-chips and 3DICs, responsible for designing with the state-of-the-art process technologies and developing corresponding CAD flows that explores cutting edge design methodologies and latest EDA tools, either for internal first-in-the-industry testchips or leading customer’s products Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.
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  • 【2026 TSMC Campus Recruitment】Design and Technology Platform Engineer (DTP)

    面議(經常性薪資達4萬元或以上) 40000元 新竹縣寶山鄉 工作經歷不拘
    【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=19034&source=1111&tags=domestic+campus+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. At the beginning of new module research, IC design engineers and R&D engineers would closely cooperate with customers. Once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time. At TSMC, you will have the opportunity to work with the most advanced module technologies, provide solutions to partners in the global IC design ecosystem, and ensure competitiveness in power, performance, and area. Responsibilities: At the beginning of new module research, IC design engineers and R&D engineers would closely cooperate with customers. Once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time. At TSMC, you will have the opportunity to work with the most advanced module technologies, provide solutions to partners in the global IC design ecosystem, and ensure competitiveness in power, performance, and area. 1. Physical Designer The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps which include floor plan, PNR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. The candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements. 2. Standard Cell Engineer (1) Pathfinding of library characterization for leading edge tech nodes. (2) Support industrial standard library kits generation and QC. (3) In-house library generation flow and/or utility development. (4) RC parasitic extraction analysis and APR related analysis. 3. Layout Engineer (1) IC layout for advanced technology (Std. cell/Memory/AMS/IO). (2) Layout structure development for new technology. (3) Pathfinding for new technology development. (4) Customer engagement and layout support. (5) Design and technology co-optimization (DTCO). (6) AI and automation for layout and physical design. 4. System and Chip Design Solutions Development Please refer to the Link: https://careers.tsmc.com/zh_TW/careers/JobDetail?jobId=516 5. FE design & DFT (1) Test chips development for advanced nodes, including physical design (APR), logic synthesis and DFT (Scan insertion + ATPG). (2) Design flow development for test chips design, which requires the programming skills, Tcl, Python, C-shell scripting etc. (3) Technology benchmarking for PPA evaluation of the advanced nodes. (4) DTCO (Design & Technology Co-Optimization) pathfinding and development. 6. SRAM Engineer (1) SRAM design in advanced nodes for mobile, high-performance computing, IoT, automotive applications. (2) RRAM/MRAM, emerging memory development. (3) In memory computing research and development. 7. Design Flow/Methodology (1) Advanced technology process design kits (PDK) and tech files (DRC, LVS, RC, etc.) development and technical support. (2) Advanced technology design development flow development and technical support. (3) Automation program development to support design kits and flow development productivity/quality. Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.
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  • CMOS Image Sensor Analog Design Engineer

    面議(經常性薪資達4萬元或以上) 40000元 新竹市 1~2年工作經驗
    【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=343&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibility: 1. Design CMOS Image Sensor (CIS) & depth sensor related test chips for process development 2. Design CIS or non-CIS test lines or test chips for process monitoring and improvement 3. Data acquisition and analysis: CIS key performance indices and random noises characterization Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.
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  • 2026 台積電校園徵才 2026 TSMC Campus Recruitment

    面議(經常性薪資達4萬元或以上) 40000元 新竹縣寶山鄉 工作經歷不拘
    【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=19032&source=1111&tags=domestic+campus+2026_1111 台積公司成立於1987年,率先開創了專業積體電路製造服務之商業模式,自此成為世界領先的專業積體電路製造服務公司。台積公司以領先業界的製程技術及設計解決方案組合支援其客戶及夥伴生態系統的蓬勃發展,以此釋放全球半導體產業的創新。身為全球的企業公民,台積公司的營運範圍遍及亞洲、歐洲及北美,致力成為企業社會責任的行動者。2024年,台積公司提供最廣泛的先進製程、特殊製程及先進封裝等不同製程技術,為500多個客戶生產超過11,000種不同產品。台積公司企業總部位於台灣新竹。進一步資訊請至台積公司網站https://www.tsmc.com.tw查詢。 因為期待無限可能,所以選擇台積。 台積致力於營造具挑戰性、可以持續學習而又有樂趣的工作環境,提供同業平均水準以上的薪酬與福利。 加入台積,您將與世界一流的優秀夥伴共事,透過最先進的製程技術,成就改變世界的大事,所有突破與創新,都有一份我們的努力。 歡迎「志同道合」的你,透過本計畫提前完成〝〝線上應徵〝〝註冊履歷,符合資格者,將享有優先面試的機會唷! 如您對台積電2026校園徵才計畫感興趣,歡迎報名參加,以掌握台積趨勢、組織概況與求職撇步。 此外,我們特別為同學安排了校園徵才實體與線上說明會,歡迎踴躍報名參加,以便了解公司市場趨勢、組織概況,並掌握求職技巧! 報名連結:請參考官網連結 (採線上報名,報名成功後將由系統自動發送活動通知信件,可重複報名不同場次。) 請線上應徵此「校園徵才活動」,如您已有求職偏好職缺,再根據以下職位額外投遞2至4個職位。 ▋歡迎志同道合的夥伴,一起加入台積 ▋世界上的每一個夢,都由我們來圓夢 Join TSMC: Where Infinite Possibilities Await. At TSMC, we believe in creating a challenging, continuous learning, and enjoyable work environment. We offer competitive compensation and benefits that exceed industry averages. Join us, and you‘ll collaborate with world-class talent, leveraging the most advanced process technologies to achieve breakthroughs that change the world. Every innovation and advancement carry the mark of our dedication. Are you ready to make an impact? We invite like-minded individuals to pre-register and submit resumes online through the 2026 Campus Recruitment Program. Qualified applicants will receive priority interview opportunities! We are organizing both on-campus recruitment and online information sessions. We encourage you to sign up for the upcoming events to gain insights into the market trends, organizational overview, and master essential interview skills. Registration Link: Click Here (Pre-registration is required – After registration, you will receive an email notification sent by the system afterwards. You may register for multiple sessions.) Please apply online for this Campus Recruitment Event. If you already have preferred job openings, you may additionally apply for 2 to 4 positions from the list below on career site. 2026 台積電校園熱門職缺 TSMC Campus Recruitment Hot Jobs : R&D (研究與發展組織)  1-1 Research and Development Engineer (R&D)  1-2 Design and Technology Platform Engineer (DTP)  1-3 Specialty Engineer (Specialty)  1-4 Integrated Interconnect and Packaging Engineer (IIP) Operations (營運組織)  2-1 Process Integration Engineer (PIE)  2-2 Process Engineer (PE)  2-3 Equipment Engineer (EQ)  2-4 Intelligent Manufacturing Engineer (IMC/MFG)  2-5 Facility Engineer (FAC)  2-6 Product Engineer (PE)  2-7 Advanced Packaging Technology & Service Engineer (APTS)  2-8 Quality & Reliability Engineer (Q&R)  2-9 Module Associate Engineer (MAE) 儲備模組副工程師  2-10 Technician 技術員 Corporate Business (策略暨支援組織)  3-1 Information Technology (IT)  3-2 Corporate Planning Organization (CPO)  3-3 Materials Management (MM)  3-4 Human Resources (HR)  3-5 Finance, Accounting and Risk Management (FIN) 營造一個合乎台積公司核心價值與經營理念的全球共融職場,對於公司未來成功至關重要。台積公司對全球共融職場的承諾,旨在讓每位員工無論性別、年齡、身心障礙、宗教、種族、族群、國籍、政治立場或性傾向,都能將其自身的觀點與經驗帶入工作,促進企業推升獲利、增加生產力並釋放創新。我們致力於創建一個公平無障礙的工作場所。台積公司承諾促進文化共融,讓每一位員工都覺得被重視且有能力為企業使命提供貢獻,並為全球各戶提供卓越服務。
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  • 數位IC設計工程師(WiFi/BT/GNSS)

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 工作經歷不拘
    無線通訊系統數位ip 設計實現
  • <Data center>HBM 記憶體數位IC設計工程師

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 2~3年工作經驗
    1. Develop and implement DRAM controller/PHY solutions for data-center applications. Validate functionality, improve design to optimize performance, power, latency and efficiency. 2. Memory controller/PHY Integration: Design and integration memory system.
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  • <Data center>數位IC設計工程師_台北 (SOC BE)

    面議(經常性薪資達4萬元或以上) 40000元 台北市內湖區 2~3年工作經驗
    1. 優化數位 IC 設計 BE 流程與方法 2. 執行與管理數位 IC 設計 BE 相關任務 (2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion (2.b) STA timing analysis 與 fixing (2.c) Netlist level QC,例如 CLP 3. 與 FE RTL designer 及 PD APR 團隊密切合作,針對 PPA(Performance, Power, Area)進行 design 及 clock structure 的優化 4. 將依應徵者的年資與專業經驗,提供不同的職級
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  • <Automotive>車用智慧座艙暨智慧型手機 SoC 數位 IC 設計工程師

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 2~3年工作經驗
    1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling
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