轉職熱搜工作

1. IC, package and PCB model extraction & co-simulation for pre-silicon SI/PI/EMC analysis. 2. SI/PI co-simulation flow development. 3. Co-work with IC designer to define specification and solve the silicon related SI and PI problems. 4. Co-work with FAE to provide SI/PI/EMC issue analysis support. 5. Engage with Computer Aided Design (CAD) tool vendors for tool evaluation and support. 『具工作經驗者，薪資另議』

1. 應用正規方法在硬體或軟體的驗證上 2. 正規方法文獻回顧與論文分析以改善目前的使用限制 3. 規劃安排跨部門的技術教學與討論課程 4. 相關的文件撰寫與審查修改 5. 此職缺之薪資起始水準為NT$29500~50000，但仍會視人選之學經歷背景調整核定。

1. 5G/6G通訊IP開發. 2. 多模(5G/6G)解調架構開發以及RTL coding/verification/integration.

1. 資料中心AI晶片架構設計與RTL實作 2. 資料中心SoC與AI運算平台設計與驗證 3. 系統匯流排與AI週邊設計 4. SoC系統效能分析

1. 優化數位 IC 設計流程與方法 (使用 AI) 2. 執行與管理數位 IC 設計 EDA 相關任務 (2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion (2.b) STA timing analysis 與 fixing (2.c) Netlist level QC，例如 CLP 3. 使用 AI 或 EDA 工具針對 PPA（Performance, Power, Area）進行優化 4. 將依應徵者的年資與專業經驗，提供不同的職級

1. SoC low power design, integration, and modeling 2. SoC adaptive voltage scaling development

We are looking for a DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality. Key Responsibilities • Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. • Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. • Perform ATPG, fault simulation, and coverage analysis. • Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. • Lead silicon bring-up and debug of test features; conduct failure and yield analysis. • Work with product teams to facilitate pattern generation, validation, and DPPM improvement.

1. SOC platform 架構與RTL implementation 2. 負責 IP/子模組之 RTL 整合，組成 SoC (System-on-Chip) 或子系統的頂層設計。 3. 依據設計規格，串接不同來源或平台的 RTL，確保各模組間介面相容與功能正確。 4. 撰寫與維護整合 RTL 的頂層模組、配置腳本及連結測試環境。 5. 針對整合後的設計進行功能模擬、靜態時序分析（STA）、Lint、CDC 及等驗證工作，並協助 debug。 6. 與軟硬體、驗證、後端設計等團隊密切合作，確保整合流程順利與產品交付時程。 7. 編寫設計文件及協助設計交付相關事務。

1. Work on AI development for design flow 2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff flow automation

1. Familiar with DFT plan, methodology, implementation 2. Familiar with new DFT flow such as SSN, HSIO 3. Familar with STA, timing analysis