轉職熱搜工作

1. Contribute to the development and enhancement of design methodologies for 2.5D and 3D IC advanced package design. 2. Lead the development of new design and signoff flows for physical, electrical, and thermal quality assurance. 3. Support package design teams in defining a tool roadmap for advanced package design. 4. Contribute to interposer designs, advanced package designs, and test vehicles for the product design roadmap and feasibility. 5. Represent the Package design team in customer engagements for advanced package designs.

1. Develop functional IP models in SystemC/TLM to enable software left-shift 2. Design clean TLM interfaces and connectivity for reusable modeling 3. Integrate IP models into a Virtual SoC (vSOC) and support system bring-up 4. Build platform-level tests and regression to validate correctness 5. Improve productivity with tooling and CI/CD automation

職責要求 RTL Coding Required • Expert-level SystemVerilog / Verilog HDL for synthesizable RTL精通 SystemVerilog/Verilog HDL，能夠寫出可綜合的 RTL 程式碼 • Deep understanding of clocking, reset strategies, and clock domain crossing (CDC) 深入理解時脈、重設策略和時脈域交叉 (CDC) • Proficient in finite-state machine (FSM) design and pipeline microarchitecture精通有限狀態機 (FSM) 設計與管線微架構 • Low-power design techniques: clock gating, power gating, multi-Vt, retention flops低功耗設計技術：時脈門控、電源閘控、多閾值電壓 (Vt)、保持觸發器 • Experience coding to timing closure constraints and meeting PPA targets具備根據時序收斂限制進行編碼並達到 PPA 目標的經驗 Microarchitecture Required • Ability to own microarchitecture spec from concept to sign-off能夠獨立完成從概念到最終定稿的微架構規範 • Strong grasp of on-chip interconnects: AXI4, AHB-Lite, APB, TileLink, CHI/ACE精通片上互連：AXI4、AHB-Lite、APB、TileLink、CHI/ACE • Cache coherency, memory subsystem, and NoC design experience具備快取一致性、記憶體子系統和片上網路 (NoC) 設計經驗 • Skilled in defining and documenting microarchitecture specification documents能夠定義和編寫微架構規範文檔 • Ability to drive design partitioning and IP integration at SoC level能夠在 SoC 層級推動設計劃分和 IP 集成 Functional Verification Required • Familiarity with UVM / OVM testbench methodology熟悉 UVM/OVM 測試平台方法 • Ability to write self-checking RTL testbenches能夠撰寫自我檢測測試RTL 測試平台 • Coverage-driven verification planning and closure覆蓋率驅動的驗證規劃與收尾 • Experience with formal property verification (JasperGold, VCFormal) 具備形式化屬性驗證經驗（JasperGold、VCFormal） Design Sign-off Required • Static timing analysis (STA) review and ECO coordination靜態時序分析 (STA) 審查和工程變更協調 • CDC / RDC lint and equivalence checking (Conformal, Spyglass) CDC/RDC 程式碼檢查和等效性檢查（Conformal、Spyglass） • DFT-aware design: scan insertion, BIST, JTAG / boundary scan考慮可設計性的設計：掃描插入、BIST、JTAG/邊界掃描 • Familiarity with PD handoff flow and P&R feedback loops熟悉 PD 交接流程和佈局佈線回饋迴路 Technical Leadership Required • Lead a team of 4–10 RTL designers across one or more IP blocks領導一個由 4-10 位 RTL 設計師組成的團隊，負責一個或多個 IP 模組 • Define and enforce RTL coding guidelines and review standards制定並執行 RTL 編碼規範和審查標準 • Mentor mid-level and junior engineers; conduct technical career development指導中級及初級工程師；進行技術職涯發展規劃 • Drive design schedule, milestone tracking, and risk identification推動設計進度、里程碑追蹤和風險識別 • Interface with DV, DFT, PD, and software teams — own design integration與設計驗證 (DV)、測試驗證 (DFT)、產品開發 (PD) 和軟體團隊對接—負責設計集成 • Represent RTL design in architecture reviews and cross-functional meetings代表 RTL 設計參與架構評審與跨職能會議 任職資格 • B.Sc in Electrical / Electronic Engineering or Computer Engineering; M.Sc preferred • 3 or more successful ASIC tapeouts in a lead or senior contributor role • Excellent written and verbal communication — able to author clear micro-arch specs • Comfortable driving cross-team technical decisions under schedule pressure • Strong debugging mindset: able to root-cause simulation failures and silicon bugs

RTL coding - Required • Proficient in SystemVerilog and Verilog HDL for synthesizable RTL精通 SystemVerilog 和 Verilog HDL，能夠寫出可綜合的 RTL 程式碼 • Solid understanding of synchronous design, clocking, and reset strategies紮實的同步設計、時脈控制與重設策略知識 • Experience with clock domain crossing (CDC) techniques and metastability handling具備時脈域交叉 (CDC) 技術與亞穩態處理經驗 • FSM coding, pipelining, and retiming for timing closure熟悉有限狀態機 (FSM) 編碼、管線和時序重整化以實現時序收斂 • Familiarity with low-power techniques: clock gating, isolation cells, retention flops熟悉低功耗技術：時脈門控、隔離單元、保持觸發器 • Writing RTL that meets area, power, and performance (PPA) targets能夠編寫滿足面積、功耗和效能 (PPA) 目標的 RTL 程式碼 Microarchitecture - Required • Ability to implement designs from a microarchitecture specification能夠根據微架構規範實現設計 • Working knowledge of AMBA protocols: AXI4, AHB-Lite, APB熟悉 AMBA 協定：AXI4、AHB-Lite、APB • Understanding of data path design, FIFOs, arbiters, and flow control logic理解資料通路設計、FIFO、仲裁器和流控制邏輯 • Familiarity with SoC integration concepts: interrupts, address maps, register files熟悉 SoC 整合概念：中斷、位址對映、暫存器文件 • Experience writing or contributing to microarchitecture specification documents具備編寫或參與微架構規範編寫的經驗文檔 Functional verification Required • Experience writing directed and self-checking RTL testbenches in SystemVerilog具備使用 SystemVerilog 撰寫定向與自我檢測 RTL 測試平台的經驗 • Familiarity with UVM methodology; ability to develop UVM agents or sequences熟悉 UVM 方法論；能夠開發 UVM 代理或序列 • Able to interpret coverage reports and drive functional coverage closure能夠解讀覆蓋率報告並推動功能覆蓋率的收斂 • Experience using simulation tools (VCS, Questa) for debug and regression具備使用模擬工具（VCS、Questa）進行調試和回歸測試的經驗 • Exposure to formal property verification (assertions, assumptions, cover points) 熟悉形式化屬性驗證（斷言、假設、覆蓋點） Design sign-off - Required • Reading and interpreting STA reports; understanding setup/hold slack and critical paths能夠閱讀和解讀 STA 報告；理解建立/保持時間裕量和關鍵路徑 • Awareness of CDC and RDC lint checks; able to resolve common violations了解 CDC 和 RDC 代碼檢查；能夠解決常見違規問題 • DFT awareness: scan chain insertion, test mode design considerations了解 DFT：掃描鏈插入、測試模式設計注意事項 • Ability to work with PD feedback and make RTL changes to resolve place-and-route issues能夠根據 PD 回饋進行 RTL 修改，以解決佈局佈線問題

職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.

1.Designs IC sockets and components using design tool provided. 2.Conduct performance forecast, simulation, and analysis 3.Modifies drawings based on NBOs. 4.Measures locally made parts and customer packages. 5.Measures IC socket and components. 6.Translates engineering documents into English (by special assignment). 7.Verifies customer package drawing to existing socket drawing. 8.Modifies and assembles parts for IC sockets. 9.Act as global engineering members. 10.Provides technical support for Sales, field support as needed. 11.Provides technical support to customers through phone, email, and on-site Work. 12.Interacts with vendors on issues of piece parts manufacturing. 13.Provides quality check for assembly and piece parts. 14.Test new products. 15.Improve design quality and speed.

1. Chip integration and quality check 2. DFT insertion, verification and scan coverage analysis 3. Synthesis and PPA analysis