轉職熱搜工作

職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.

1. Bus and Architecture design and RTL implementation of Smartphone chipset 2. ASIC and Smartphone SoC and mobile computing platform design. 3. System bus and mobile peripheral designs 4. SoC system performance analysis

我們正在招募一位熟悉生成式AI技術且擅長前端數位設計的工程師。本職缺專注於運用前沿商業或開源 LLM，於RTL設計、RTL優化、simulation testbench生成、formal testbench 生成等數位設計流程，開發提升設計自動化與效率之 AI 演算法。您將與RTL設計工程師、DV驗證工程師與AI專家合作，共同推動數位設計智能化。另外, 您也會研讀期刊,開發並評估效果, 並撰寫技術文件,專利或paper投稿.

1.AI系統硬體規劃：系統規格與設計需求收集 2.AI系統硬體設計：負責設計和開發硬體系統架構，包括電路設計、元件評估與選擇、客製化元件規劃。 3. AI系統硬體驗證與測試：確認硬體系統正常運作，包含驗證與測試。 4. 跨組織合作：與IC design team、system team、SI/PI team與layout team等等合作，完成系統設計、製作與驗證。 5.客戶與相關廠商支援：包含技術文件撰寫、客戶參考設計支援、on site支援等等。

高速類比SerDes電路全客製化佈局設計及自動化流程設計 Fully custom layout design for analog high-speed SerDes circuit and layout automation flow development.

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification. * (If manager) Manage the design architecture team, focusing on both technological advancement and talent development.

我們正在重新定義晶片設計的未來，不再僅僅是設計電路，而是打造一個能夠「自我演化」的晶片設計大腦。我們正在招募具備 IC 設計與 AI 技術熱忱的工程好手，一起開創 IC 設計新時代！您將與跨領域專家攜手打造 IC Design Autonomous 的未來——運用最先進的 GAI 技術，實現從規格生成、RTL 編碼到自動化 QC 錯誤清除的完整 IC 生命週期自動化，並建立自我進化的生產力循環，讓 AI 真正落地於 IC 設計流程！ *任務描述 - 全流程自動化：設計並實作端到端的自主設計代理人 (Agentic AI) 框架，涵蓋 Spec-to-RTL 與自動化 QC 修復 - 架構演進：利用 GAI 技術進行 PPA (Power, Performance, Area) 優化，開發具備自我回饋、自我學習能力的設計閉環 - 技術領導：指導跨團隊協作，將 IC 設計流程中的自動化瓶頸，轉化為 AI 可理解並自主執行的架構 - 知識體系建構：構建領域專屬的 Knowledge Base 與 Multi-Agent 協作框架 - 研究創新：研讀最新技術、發表專利論文，將前沿研究轉化為實際應用

We are looking for a highly skilled DFT CAD and Methodology Expert to develop and deploy advanced test methodologies for next-generation data center and AI ASIC. Enhancing the efficiency and quality of our ASIC development and testing procedures. The successful candidate will work within the CAD team to innovate test solutions for complex 2.5D/3DIC, ensuring high quality and yield for advanced packaging technologies. Key Responsibilities • Methodology Development: Develop and deploy robust CAD flows for scan insertion, ATPG, pattern simulation, and Memory BIST (MBIST). • Tool Automation: Create scripts (Python, TCL, Perl) to enhance and automate DFT flows, accelerating simulation runtimes and improving quality of results (QOR). • EDA Tool Integration: Collaborate with EDA vendors to enhance tools for advanced packaging, including test verification and pattern generation. • Support & Debug: Support DFT integration teams with CAD flow issues, debug complex issues, and provide technical mentorship. • 3DIC/2.5D Expertise: Develop and implement testing strategies for chiplets and TSV-based 3D stacks. • Location: Hsinchu, Taipei, Singapore.