轉職熱搜工作

1. Chip integration and quality check 2. DFT insertion, verification and scan coverage analysis 3. Synthesis and PPA analysis

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis 2. Basic knowledge of analog design 3. Mixed signal design experience is a plus. 4. SoC architecture exploration and performance analysis experience is plus. 5. Post-silicon mass production experience ((Ex: DFT, CP, FT)) is a plus. 1 . 熟悉數位IC整合流程, 包含RTL, 模擬, 時序分析, 功耗分析, 2 . 具類比IC設計的基本知識 3. 混和訊號IC設計經驗是加分項 4 . 系統架構分析經驗是加分項 5 . 具IC量產相關經驗(Ex: DFT, CP, FT)是加分項

1. 定義供電架構並開發硬體/軟體協同設計技術與策略，以優化系統的電源效能。 2. 設計微處理器控制器和硬體電路，以及用於智慧型手機與車用產品電源控制相關設計的硬體輔助方案。 3. 進行耗電與時鐘樹分析，以發掘電源優化的機會。

1. 數位 IC 設計（RTL/電路合成/整合/驗證） 2. SoC 層級晶片設計/整合 3. DFT 相關設計/規劃/整合 4. 靜態時序分析以及收斂 5. 設計流程開發與最佳化 6. 工作地點：台北/新竹

車用IC 於座艙系統的硬體PCB module應用開發事項，針對SOC system on module board 的PCB 開發。負責PCB Module 的電路設計，Layout 相關的review, 並基於Module 的DFM rule產出相關的設計文件。

1. Make test pattern plan to cover system bring-up for MP (CP/FT, system test, DVT, HQA, correlation, DPPM reduction) 2. Debug post-silicon issue to identify design weakness and solution finding 3. Correct post-silcion measurement vs. pre-silicon simulaiton, including process, performance, power.

- 負責資料中心相關 IP 整合，涵蓋從合成、DFT 至 GDS 交付完整流程 - 負責先進製程晶片整合，涵蓋從synthesis QC Sign-off & Tapeout

- Optimize GPU performance, area/power for representative workloads (graphics and compute) from the perspectives of memory sub-system, low-power design/policy and implementation strategy. - System modeling framework to simulate hardware with different accuracy/throughput tradeoffs at different stages of the design; supervise Performance/Power/Area investigation/validation and facilitate architecture/design decisions

- Collaborate with architects and cross-functional teams to understand GPU specs and define verification strategies. - Develop SystemVerilog/UVM test frameworks and co-simulation environments; verify GPU logic at unit, subsystem, and top levels. - Create and execute verification test plans, focusing on functional coverage. - Generate random and directed test sequences; maintain testbench, scoreboard, BFMs, and regression. - Perform RTL and coverage analysis; optimize test scenarios and address bug escapes. - Support performance verification, emulation, data collection, debugging, and PPA improvements. - Conduct formal verification.

Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.