轉職熱搜工作

1. CPU system design and performance analysis 2. AMBA System bus architecture and integration 3. IP and system design and verification

1. Direct manager and project lead 2. Cloud data center product 3. DFT task force 4. short term: top DFT flow implement and signoff long term: DFT/test mode planning and new tech development.

車用電源系統，車用電子，12V or 48 V 等產品的系統電源設計/驗證之電源應用工程師，需與Designer 、PM、SW 等單位討論系統的電源設計的競爭力的分析，並驗證系統Power solution，撰寫design note 等文件，協助處理客戶開案並量產的相關系統電源問題。

在系統級封裝（SiP）與 PCB 佈局的極早期階段，就將 EMC 對策融入設計中。您將與 IC 設計、封裝、軟韌體及功能安全（ISO 26262）團隊緊密合作，確保我們的產品能一次性通過全球最嚴苛的 Tier-1 與車廠認證標準。 關鍵工作內容 (Key Responsibilities) 1. 系統設計 (Board Co-Design for EMC)： • 設計與優化電源分配網路（PDN），制定去耦電容（Decoupling Capacitor）的佈局與選型策略，從源頭降低電磁輻射（EMI）與提升耐受性（EMS）。 2. 先進電磁模擬與預測 (Advanced EM Simulation)： • 在投片（Tape-out）與洗板（PCB fabrication）前，利用 3D 電磁模擬軟體（如 Ansys, CST）進行系統級的輻射與傳導雜訊模擬分析，提前發現並消除潛在的 EMC 風險。 3. 車規標準合規與驗證 (Automotive Standard Compliance)： • 確保產品符合全球車規 EMC 標準，包含 CISPR 25, ISO 11452, ISO 7637, ISO 16750 以及各大車廠（OEM）的客製化規範。 • 將系統級（System-level）的車規要求，向下拆解並定義為 IC 與 SiP 模組級（Component-level）的設計規格。 4. 實驗室除錯與跨部門技術指導 (Debugging & Cross-functional Leadership)： • 帶領團隊在無響室/電波暗室進行產品測試。當面臨 EMI/EMS 挑戰時，能迅速進行根因分析（Root Cause Analysis）。 • 提出軟硬體整合的解決方案（例如指導韌體團隊設定 Spread Spectrum Clocking, SSC 展頻技術，或調整硬體濾波器），並驗證其有效性。

We are looking for talented engineers to join our GPU Architecture team. In this role, you will be at the forefront of defining the next generation of mobile high-performance GPUs. You will be responsible for developing a C++ based model, which serves as the primary tool for architectural exploration, bottleneck analysis, and performance projection before silicon availability. Whether you are a fresh graduate with a strong passion for computer architecture or a seasoned veteran in performance modeling, we invite you to help us push the boundaries of graphics rendering and compute efficiency.

1. USB3 Controller Maintainess/Development 2. Short term =＞ Handle the USB3 Controller for different projects and adding new features. Long term =＞ Co-work with USB4 team to co-develop the next gen USB4 controller

Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting

Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

1. TOP 設計包含：微架構、設計、模擬、測試 - DFT top, PAD top 2. TOP 和感測器的整合和模擬包含： - eFUSE - PVT 感測器和 aging 感測器 - 整合 IO 到晶片中並滿足客戶需求 3. 測試流程、環境和程式開發