轉職熱搜工作

•重點開發技術: 系統軟韌體開發、高速資料實體層(physical layer) 資料傳輸軟體開發、優化硬體效能及產品量產品質控管 •主要目標: 完成Enterprise/AI/xPU等相關產業客製化IC的軟韌體開發與系統整合，並協助客戶產品量產 •負責新產品的系統設計與開發，確保符合公司及客戶的需求 •協助量產過程中的技術問題解決，並提供專業建議以提升生產效率與品質 •與跨部門團隊合作，確保產品從設計到量產的順利過渡 •分析並改善現有系統和流程，以提高產品質量和生產效率 •參與產品測試和驗證，確保產品符合相關標準和規範

我們正在尋找一位同時精通 AI 與晶片設計的專家，能夠將人工智慧技術應用於晶片設計流程，提升生產力與產品品質。此職位需要具備 IC 設計知識，以及機器學習／生成式 AI 的專業能力，能夠主動發掘並定義創新機會，設計可行且穩定的解決方案，並優化設計流程。若您對先進製程開發或類比設計有相關經驗，將會是加分項目。 我們歡迎對跨領域創新充滿熱情、喜歡處理複雜資料並挖掘洞見、勇於挑戰的工程師或資料科學家加入我們的小型多元團隊。您將透過快速迭代，為 MediaTek 的晶片設計流程提供最合適的 AI 解決方案。 軟實力方面，您需具備主動積極的態度、持續學習與適應新知的能力、優秀的溝通技巧，以及跨部門協作的能力。硬實力方面，您需擁有扎實的程式設計能力，並具備足夠的 IC 設計與 AI 技術知識。

As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line verification plan. It included: integrated simulation/verification env development, big data analysis and efficiency improvement, bus fabric / EMI (External memory interface ) / Low power functions verification plan and implementation Need to build up verification plan/bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone/ASIC operating schemes Need to leverage the latest EDA tool and concept to accomplish the verification plan Work location: Hsinchu/Taipei

1. Familiar to 2.5D or 3D PKG integration & development & mass production experience 2. From chip architecture view to propose best-fit PKG technology with SIPI, testing, thermal consideration

-規劃並執行高速介面（如 PCIe, USB, DP, UFS, CSI, UCIe）IP PHY 驗證。 -建立並維護測試平台，進行 System 與 Electrical 測試。 -使用 Scope, BERT, LA, Signal Analyzer 等儀器進行 Signal Integrity 與 Compliance Test。 -分析測試結果，協助 DE 及 SW 團隊解決問題。 -設計並開發硬體 PCB 評估板，支援系統驗證。

1. Develop high speed interface subsystem architecture and integrate PCIe, MIPI, or DisplayPort subsystem. 2. Develop security and FuSa function on PCIe, MIPI, or DisplayPor degital circuit.

1. Serdes/High speed interface related PHYD IP architecture planning. 2. Serdes/High speed interface related PHYD IP RTL coding. 3. Serdes/High speed interface related PHYD IP front-end and back-end integration. 4. Co-work with MAC design team and DV team for IP verification. 5. Co-work with Analog design team for PHY co-simulation.

Design the 5G and next-generation modem processor with cost effective, high speed, and low power hardware performance. This position will develop the modem processor that optimized for modem system. Co-work closely with software and system architecture colleague to analysis the sweet point of system performance and low power. In this position, you will push the physical performance to next level and co-work with place-and-route (PAR) team resolving the bottleneck of speed and power.