轉職熱搜工作

Joining in specification definition, designing verification platform, developing behavioral models, and responsible for system and functional verification

Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools. 5. Good communication and team working skills. 6. Experience in handling large scale SoC chip implementation is a plus.

工作項目： SSD專案 Leader，帶領團隊開發 SSD產品。 應徵條件： 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程相關科系畢業為主。 2. 具5年以上相關工作經驗： (1) 精通 SATA interface protocol. (2) 精通 PCIe interface protocol. (3) 精通 NAND flash protocol. (4) 精通 LDPC演算法。 (5) 精通 Digital design流程或具其他相關經驗者為佳。

工作項目： 1. SOC integrator! A challenging job for integrating the designs from over 100 digital designers and tens of analog designers. A challenging job of using deep submicron process. 2. Building & Improving the standard environment for digital designers to run front-end flow, such as synthesis, STA analysis, linting, and so on. 3. Cooperating with APR designers for backend timing closure. 4. Block / Whole-Chip CTS (Clock-tree Synthesis) analysis and improvement. 應徵條件： 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程等相關科系畢業為主。 2. 熟悉 verilog, verdi, STA, synthesis. 3. 具 CTS(Clock tree synthesis) Design/Debug經驗者尤佳。 4. 會寫 script如 perl者更佳。 5. 具六年以上相關工作經驗。

1. Substrate線路佈局與設計。 2. 熟悉 Cadence Allegro APD軟體操作 。 3. 負責設計產品 : 智慧型手機 (國際品牌一線大廠)、可移動穿戴式裝置 (Smart galss / Smart watch)、大尺寸液晶螢幕電視、與最先進的3C產品。

應變能力： 針對主機異常能快速診斷 標準化執行： 依照現行設備調整設定，確保 TCP/FTP 傳輸順暢。 現場與遠端： 處理各縣市設備的架接與調校。 職缺條件描述： 具備基礎Linux 系統操作與網路架構 具備基礎 Python 或 C++ 閱讀與修改能力 了解 TCP/IP、FTP 等通訊協議實作。 具備獨立排查硬體與系統問題的邏輯思考能力。

1.CoWoS large FCBGA製程導入評估、驗證及製程改善及tooling 設計經驗。 2.負責FCB/TCB 相關製程及flux材料開發，或heat sink, ball mount 相關製程及 thermal conductive material 材料開發。 3.專案執行與規劃。

1. Molding process evaluation/prediction/suggestion/optimization. 2. Molding material (thermal set) propoties, non-newton flow fluid analysis. 3. Legends/Advanced Packaging simulate technologies development.