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  • 中央系統驗證技術研發工程師

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 工作經歷不拘
    工作項目: 1. 研發/導入Emulation/Prototyping技術。 2. Emulation Performance Optimization. 3. Validation Flow Optimization. 4. 自動化程式開發。 應徵條件: 1. 碩士; 電機工程、資訊工程相關科系畢業為主; 兩科系/領域都有學歷者佳。 2. 熟悉 Synopsys Zebu/HAPS or Cadence Palladium/Protium者佳。 3. 熟悉 IC Validation Flow or Software Bring Up Flow者佳。 4. 熟悉自動化 script語言(Ex: Python)者佳。
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  • 高效能運算(HPC)Sign-off & Silicon資深工程師T1

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 工作經歷不拘
    工作項目: 1. High-Performance CPU/GPU Timing & Power Integrity Signoff 2. High-Performance CPU/GPU Post-Silicon Validation & Debug, Sim-to-Silicon Correlation 3. 協同開發 CPU/GPU Advanced DFT, On-Chip PVT Sensor, Performance Improvement & Power Management 等先進技術 4. 支援產品 SoC Projects,協同執行 High-Performance CPU/GPU 專案開發,導入先進 IP 及技術 應徵條件: 1. 碩士以上;電機、資工、電子相關科系畢業為主。 2. 熟悉 SoC Integration & Design Flow、Frontend/Backend/DFT/Timing/IR Drop/Power Analysis EDA Tools。 3. 有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 4. 有 Chip-Level, Package & PCB Power Integrity Optimization 經驗尤佳。 5. 有On-Chip PVT Sensor 開發經驗尤佳。 6. 有Post-Silicon Validation, Debug 及 RMA 分析經驗尤佳。 7. 積極負責、溝通協調能力強、勇於迎接挑戰,對於 High-Performance CPU/GPU Technology 有興趣者。
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  • 高效能運算(HPC)處理器軟體工程師T1

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 工作經歷不拘
    工作項目: 1. Software and utility development for ARM Architecture based Complex CPU Subsystem Platform 2. CPU function validation and testing software development 3. CPU post-silicon issue analysis, debug & resolving 應徵條件: 1. 碩士以上; 資訊工程、資訊科學、電機工程、電子工程等相關科系畢業。 2. 熟悉 ARMv7/v8/v9-A CPU 架構,有 ARM Cortex-A CPU system software 經驗尤佳。 3. 熟悉以下經驗者: (a) CPU 之系統程式或工具開發。 (b) CPU/OS之 debug 及問題分析。 (c) CPU post-silicon issue analysis, debug & resolving。 (d) 具備 Verilog RTL 及相關工具軟體開發經驗。 4. 積極負責、溝通協調能力強、勇於迎接挑戰,對於 High-Performance CPU Technology 有興趣者。
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  • Ethernet Switch硬體系統資深工程師(PAM4 Serdes)

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 5~6年工作經驗
    工作項目: 200G/400G/800G Ethernet Switch硬體系統設計。 應徵條件: 1. 學士以上; 電機、電信、電控、電子、資訊、通訊等相關科系畢業為主。 1. 具5年以上高速 Ethernet Switch(200G/400G/800G/PAM4)硬體系統設計開發驗證經驗。 2. 熟悉高速訊號系統 NRZ與 PAM4 Serdes量測或模擬,與 compliance驗證流程之實務經驗。 3. 具制定與執行高速介面 NRZ/PAM4 serdes test plan之能力。 4. 具備機架式產品或伺服器/資料中心 module產品經驗尤佳。 5. 具備各種高速 Serdes介面,如 PCIE4.0/5.0/6.0、USB3.1/4.0之產品實作測試經驗尤佳。 6. 具備理解 IC內部不同介面運作原理、debug或參數調整能力尤佳。 7. 具備理解 PAM4 DSP架構運作原理與處理實務之能力尤佳。 8. 熟悉 OrCAD、PowerPCB/Allegro Layout。
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  • Camera演算法開發工程師/專案技術主管

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 3~4年工作經驗
    工作項目 : 1. Camera ISP影像處理及3A演算法開發。 2. Computer Vision (CV)電腦視覺演算法開發。 3. Artificial intelligence (AI) 機器學習演算法開發。 4. 帶領小組團隊研發。 應徵條件: 1. 碩士以上;電機電子工程相關、資訊工程相關。 2. 熟悉常用程式設計語言如C/C++/Matlab。 3. 具訊號處理或IC設計工作經驗者為佳。
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  • Camera演算法開發工程師/專案技術主管(臺北大直)

    面議(經常性薪資達4萬元或以上) 40000元 台北市中山區 3~4年工作經驗
    工作項目 : 1. Camera ISP影像處理及3A演算法開發。 2. Computer Vision (CV)電腦視覺演算法開發。 3. Artificial intelligence (AI) 機器學習演算法開發。 4. 帶領小組團隊研發。 應徵條件: 1. 碩士以上;電機電子工程相關、資訊工程相關。 2. 熟悉常用程式設計語言如C/C++/Matlab。 3. 具訊號處理或IC設計工作經驗者為佳。
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  • SoC Verification Engineer

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 工作經歷不拘
    1.Writing behavioral model 2.Responsible for functional verification
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  • Senior SoC Verification Engineer

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 2~3年工作經驗
    Joining in specification definition, designing verification platform, developing behavioral models, and responsible for system and functional verification
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  • (Germany) Sr. Field Application Engineer – Automotive Ethernet

    面議(經常性薪資達4萬元或以上) 40000元 中歐德國 3~4年工作經驗
    1. Summary Realtek Semiconductor Corp., located in the Hsinchu Science-based Industrial Park, Taiwan‘s 〝Silicon Valley〝, established in 1987. Realtek‘s efforts to provide the ultimate in pioneering IC technology — along with its firm commitment to creating unique and innovative designs for a broad range of high-tech applications — have won the company a worldwide reputation and made possible a favorable and consistent growth rate in the years since its establishment. In line with the Realtek culture of 〝Self-confidence and trust in people〝, we believe that we can achieve our best, and trust our colleagues can also do the same. Working and learning in Realtek, we openly share knowledge and experience with one another to inspire innovation and pursue growth of the company, as well the individuals. Talent is the important capital of Realtek. Welcome to Join Realtek Family! 2. Essential Job Functions ‧Locate in Southern part of Germany (Frankfurt to Stuttgart, or Stuttgart to Munich) ‧Provide pre-sales and post-sales support. ‧Understand customer requirements, and deliver technical presentations, reports, documents and technology demonstrations. ‧Support customer product development and design. ‧Support customer issue analysis and resolve. ‧On-site support for debug or certification test. ‧Cross-functional collaboration with Realtek internal resources. 3. Education, Skills, Abilities, And Experience Required ‧M.S. or B.S. in Engineering or equivalent. ‧3 to 5 years of progressive professional technical experience in IC design or related areas, direct experience in IC design house FAE is preferred. ‧Strong analytical and problem solving skills. ‧Strong written/verbal communication and negotiation skills. ‧Being proactive and willing to take initiatives. ‧Ability to work independently to achieve goals. ‧Ability to understand and explain technical issues and solutions to technical and non-technical personnel. ‧Native German skill. ‧Medium or higher English skill. ‧Familiar with Ethernet protocols will be a plus. ‧Familiar with Automotive ecosystem will be a plus. ‧Basic or higher Chinese skill will be a plus. ‧Experience of Linux system will be a plus. 4. Industry Automotive Ethernet, Semiconductor 5. Employment Type Full-time 6. Job Functions Engineering, Business Development
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  • Senior Physical Design / APR Engineer / APR Manager(新竹)

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 5~6年工作經驗
    Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools. 5. Good communication and team working skills. 6. Experience in handling large scale SoC chip implementation is a plus.
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