轉職熱搜工作

1. Develop high speed interface subsystem architecture and integrate PCIe, MIPI, or DisplayPort subsystem. 2. Develop security and FuSa function on PCIe, MIPI, or DisplayPor degital circuit.

1. Define power states and management hardware architecture for optimal power performance. 2. Design microprocessor-based power management controller and HW assistance designs. 3. Define power architecture by performing power rail tradeoff analysis with adaptive voltage scaling consideration

1. 具備先進製程SoC 晶片 top flow 的專業知識。 2. Advance CTS design 3. 開發先進制程的 Power Mesh 經驗。

1. Smartphone (Low Power Architect) and Automotive (Power control) 2. Not a management position 3. Short term:digital IP design/integration of power control IPs with zero bugs Long term:define power control arch for smartphone or automotive products develop new tech for power control

Requirements Elicitation, Requirements Analysis, and Architectural Design - Analyze product requirements from customer - Discuss the expectations and requests with customer - Agree or reject the requirements - Make architectural design proposals

1. Familiar with HSIO spec (PCIE, USB, UFS, DP, ...etc) and system usage scenario 2. Familiar with Windows and Android OS 3. Experienced with PC south bridge design 4. Experienced with PC USB host chipset design

This position involves developing memory architectures, creating circuit implementation techniques and be an interface with CAD team for full verification and model generation. You have opportunity to know how memory design can be implemented into all Mediatek products.

* Define and optimize SOC hardware architecture and associated software flows in aspects of system performance/power/area to improve MediaTek‘s product competitiveness. * Develop simulation and analysis platforms for performance/power/area analysis. * Work Loction : HsinChu, Taipei

1.從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 2.產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 3.執行或協助功秏量測, 與power model預估的功秏做校正 4.分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 5.提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗