轉職熱搜工作

1. Develop and implement DRAM controller/PHY solutions for data-center applications. Validate functionality, improve design to optimize performance, power, latency and efficiency. 2. Memory controller/PHY Integration: Design and integration memory system.

1. 優化數位 IC 設計 BE 流程與方法 2. 執行與管理數位 IC 設計 BE 相關任務 (2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion (2.b) STA timing analysis 與 fixing (2.c) Netlist level QC，例如 CLP 3. 與 FE RTL designer 及 PD APR 團隊密切合作，針對 PPA（Performance, Power, Area）進行 design 及 clock structure 的優化 4. 將依應徵者的年資與專業經驗，提供不同的職級

We are looking for AI hardware architect/designer to join our team and play a pivotal role in designing, developing, and optimizing architecture of the neural processing unit (NPU). As an architect/designer, you will be responsible for creating innovative hardware and software solutions that meet the performance, scalability, and efficiency requirements of our advanced NPU environment. The ideal candidate will have a strong background in computer architecture, microarchitecture, and digital design, as well as experience with industry-standard tools and methodologies. You are expected to transform novel ideas into practical proposals for future NPU products, and vet the proposals via prototyping. Extensive knowledge in compiler and operating system is a plus. International travel may be required.

1. Serdes/High speed interface related PHYD IP architecture planning. 2. Serdes/High speed interface related PHYD IP RTL coding. 3. Serdes/High speed interface related PHYD IP front-end and back-end integration. 4. Co-work with MAC design team and DV team for IP verification. 5. Co-work with Analog design team for PHY co-simulation.

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

1. 旗艦智慧型手機晶片整合 2. 車用系統晶片整合 3. Clock架構 4. Timing收斂與分析 5. DFT/Test mode整合驗證

無線通訊設計驗證 包含 Test plan 規劃, Bench, VIP 建立, test case 撰寫, 完成coverage等相關驗証工作

1. 新產品開發討論 2. 電源管理IC及電源管理單元晶片整合 3. 與設計/生產/品保/軟體部門溝通協調 4. 晶片開發滿足智慧手機, IOT, 車用, 以及ASIC的需求

1. (內轉佳, 提供發揮舞台, 跨產品線工作流程最佳化) 2. 人格特質: 領導力, 積極正面帶領團隊完成任務 3. 工作範圍:數位SOC設計整合, 包含 - Package, Floorplan, IOMUX, Test-mode design - Clock/CTS/reset/mixed-mode/DFT architecture, design and verification - RTL design and deliver SDC according to IP spec and requirement - SOC/IP DCT/DCG/Fusion synthesis - STA/CDC/CCD/TV/LEC/nLint/CLP tool and task handling