轉職熱搜工作

1. Serdes PMA IP architecture planning 2. Serdes PMA IP RTL coding 3. Serdes PMA IP front-end and back-end integration 4. Co-work with PCS and MAC design team and DV team for IP verification 5. Co-work with Analog design team for PHY co-simulation 6. Co-work with Algorithm team for algorithm implementation and bit-true verification

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

1. 旗艦智慧型手機晶片整合 2. 車用系統晶片整合 3. Clock架構 4. Timing收斂與分析 5. DFT/Test mode整合驗證

1. 規劃NPU量產測試程式 2. 測試及驗證IC功能、性能以及功耗的分析改進 3. 分析測試資料及測試相關問題，並分析良率問題並改善 4. AVS low power 的設計

1. (內轉佳, 提供發揮舞台, 跨產品線工作流程最佳化) 2. 人格特質: 領導力, 積極正面帶領團隊完成任務 3. 工作範圍:數位SOC設計整合, 包含 - Package, Floorplan, IOMUX, Test-mode design - Clock/CTS/reset/mixed-mode/DFT architecture, design and verification - RTL design and deliver SDC according to IP spec and requirement - SOC/IP DCT/DCG/Fusion synthesis - STA/CDC/CCD/TV/LEC/nLint/CLP tool and task handling

1. Supplier Management: Manage key substrate suppliers and conduct rigorous QCDST evaluations to ensure alignment with MediaTek‘s standards. 2. Capacity & Supply Planning: Monitor substrate market dynamics (focusing on ABF) to secure long-term capacity reservations and strategic allocations. 3. Risk Mitigation: Track upstream raw materials (e.g., CCL, T-glass fiber) and cultivate 360-degree relationships with key vendors to prevent supply disruptions. 4. Cost Optimization: Drive cost-reduction targets through in-depth cost structure analysis, process optimization, and quarterly/annual price negotiations. 5. NPI & Technology Alignment: Partner with Package Design and R&D during the NPI phase to evaluate supplier technology roadmaps and mass-production feasibility. 6. Cross-functional Issue Resolution: Collaborate internally to expedite solutions for material shortages, quality excursions, and urgent order modifications. 1. 供應商管理： 管理主要的基板供應商，並進行嚴格的 QCDST（品質、成本、交期、服務、技術）評估，以確保其符合聯發科的標準。 2. 產能與供應規劃： 監控基板市場動態（特別是ABF基板），以確保長期產能預留以及策略性分配。 3. 風險控管： 追蹤上游原材料（如CCL、T玻纖），並與主要供應商建立全方位的夥伴關係，以預防供應中斷。 4. 成本優化： 透過深入的成本結構分析、流程優化，以及季度／年度價格談判，推動達成成本降低目標。 5. 新品導入與技術協同： 在新品導入（NPI）階段，與封裝設計及研發部門合作，評估供應商的技術藍圖與量產可行性。 6. 跨部門問題解決： 內部協作，快速解決原物料短缺、品質異常與緊急訂單變更等問題。

1. AI處理器, DSP, 和相對應的周邊IP驗證環境開發 2. 從module到IP的功能驗證及自動化環境 3. Formal技術探討及實作 4. 設計測試pattern以對低耗電及效能做分析 5. Post-silicon 除錯 及 耗電/效能correlation

1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution