轉職熱搜工作

負責設計並優化數位相機及影像信號處理領域之IC，與演算法團隊協作，共同開發領先業界的影像處理解決方案，應用於智慧型手機、平板、車用及家庭娛樂等高成長市場。 工作職責 : - 與演算法工程師協作，設計高效能影像信號處理（ISP）/電腦視覺（CV）電路 - 提供優化硬體方案，達成IC設計「黃金三角」：最小矽面積、極低功耗、最佳影像品質 - 負責RTL設計、模擬、驗證、邏輯合成與整合流程 - 參與專案系統架構與技術研討，提出創新設計方案 - 支援產品跨部門整合及技術溝通

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis 2. Basic knowledge of analog design 3. Mixed signal design experience is a plus. 4. SoC architecture exploration and performance analysis experience is plus. 5. Post-silicon mass production experience ((Ex: DFT, CP, FT)) is a plus. 1 . 熟悉數位IC整合流程, 包含RTL, 模擬, 時序分析, 功耗分析, 2 . 具類比IC設計的基本知識 3. 混和訊號IC設計經驗是加分項 4 . 系統架構分析經驗是加分項 5 . 具IC量產相關經驗(Ex: DFT, CP, FT)是加分項

1. Supplier Management: Manage key substrate suppliers and conduct rigorous QCDST evaluations to ensure alignment with MediaTek‘s standards. 2. Capacity & Supply Planning: Monitor substrate market dynamics (focusing on ABF) to secure long-term capacity reservations and strategic allocations. 3. Risk Mitigation: Track upstream raw materials (e.g., CCL, T-glass fiber) and cultivate 360-degree relationships with key vendors to prevent supply disruptions. 4. Cost Optimization: Drive cost-reduction targets through in-depth cost structure analysis, process optimization, and quarterly/annual price negotiations. 5. NPI & Technology Alignment: Partner with Package Design and R&D during the NPI phase to evaluate supplier technology roadmaps and mass-production feasibility. 6. Cross-functional Issue Resolution: Collaborate internally to expedite solutions for material shortages, quality excursions, and urgent order modifications. 1. 供應商管理： 管理主要的基板供應商，並進行嚴格的 QCDST（品質、成本、交期、服務、技術）評估，以確保其符合聯發科的標準。 2. 產能與供應規劃： 監控基板市場動態（特別是ABF基板），以確保長期產能預留以及策略性分配。 3. 風險控管： 追蹤上游原材料（如CCL、T玻纖），並與主要供應商建立全方位的夥伴關係，以預防供應中斷。 4. 成本優化： 透過深入的成本結構分析、流程優化，以及季度／年度價格談判，推動達成成本降低目標。 5. 新品導入與技術協同： 在新品導入（NPI）階段，與封裝設計及研發部門合作，評估供應商的技術藍圖與量產可行性。 6. 跨部門問題解決： 內部協作，快速解決原物料短缺、品質異常與緊急訂單變更等問題。

1. High Speed digital design implementation 2. Integration from RTL to gate level, including flow QC, timing closure and issue analysis & solving 3. Signoff on design with mixed-signal interface 4. Design methodology and integration flow improvement

The candidate will conduct functional verification of the RF transceiver circuit design at various stages—from individual circuit blocks to the complete system operation—using behavioral models during the design process.

1. 規劃NPU量產測試程式 2. 測試及驗證IC功能、性能以及功耗的分析改進 3. 分析測試資料及測試相關問題，並分析良率問題並改善 4. AVS low power 的設計

1. Work on 2~4nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

Co-work with algorithm, digital/analog design, firmware, AI tool teams. 0+ ~ 10+ Years Experience in: Agentic AI Workflow/Tool Evaluation/Deployment Data Center & High-Speed SerDes Design Verification Plan & Project Execution Automotive Design Verification Plan & Project Execution 5G/6G Wireless Communication Design Verification Plan & Project Execution Satellite/NTN Communication Design Verification Plan & Project Execution Processor Platform/Peripherals Design Verification Plan & Project Execution Subsystem / System Level Design Verification Plan & Project Execution

根據不同專案使用的各種CPU架構: * Function validation * Margin characterization & validation * System stability validation * Power/VF/Benchmark characterization * Customer issue resolve