轉職熱搜工作

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

1. Develop systematic algorithms to alleviate design challenges, including implementation, process what-if assessment, system performance evaluation, in advanced nodes or package 2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies 3. Explore new EDA features and define improvement direction from MTK product requirements

* Define and optimize SOC hardware architecture and associated software flows in aspects of system performance/power/area to improve MediaTek‘s product competitiveness. * Develop simulation and analysis platforms for performance/power/area analysis. * Work Loction : HsinChu, Taipei

1. Collaborate with engineers to understand product specifications and assist in writing detailed, high-quality English documents that meets customer requirements. 2. Edit English technical documents to maintain content consistency and quality, and ensure that the documents comply with MediaTek’s documentation standards. 3. Verify the English content output by AI tools. 4. Develop project workflows. 5. Document quality management and develop improvement plans. 1. 與工程師合作，瞭解產品規格，協助產出內容詳盡、高品質、符合客戶要求的英文技術文件。 2. 編修英文技術文件，維持內容一致性和品質，並確保文件符合聯發科技文件規範 3. 驗證AI工具輸出之英文內容 4. 制訂專案工作流程 5. 文件品質管理和制訂改善計畫

1. Bus and Architecture design and RTL implementation of Smartphone chipset 2. ASIC and Smartphone SoC and mobile computing platform design. 3. System bus and mobile peripheral designs 4. SoC system performance analysis

1. Architecture design and RTL implementation for Smartphone and automotive chip 2. Smartphone SoC and mobile computing platform design. 3. System bus and high speed interface designs

設計以資料中心和人工智慧產品為導向的高速Serdes連接PHY架構。該職位的主要職責是為世界級客戶設計並交付ASIC產品。您將參與打造低功耗、高性價比且高速的Serdes PHY設計。您將有機會拓展視野，與來自多個國家的同事合作。此職位所需的專業知識包括數位通訊設計（均衡器、有限脈衝響應濾波器）、類比設計（鎖相環、類比數位轉換器、校準）和系統單晶片（SoC）設計（微控制器、匯流排協定）。

1. 5G/6G通訊IP開發. 2. 多模(5G/6G)解調架構開發以及RTL coding/verification/integration.

1. 旗艦智慧型手機晶片整合 2. 車用系統晶片整合 3. 晶片整合流程與自動化程式設計 4. Timing收斂與分析 5. SoC Floorplan架構設計 6. SoC Clock架構設計