轉職熱搜工作

笠登工程有限公司擁有多年的專業技術與經驗，專注於高科技半導體產業的自動化倉儲設備安裝，並以高效率及高品質的服務深受客戶肯定。我們的目標是透過創新的技術解決方案，助力高科技產業提升產能與效能，為科學園區的科技大廠提供頂級服務，成為業界的領導者。 工作內容： 1. 負責空調及水機電系統相關工程的施工品質監督與現場檢查，確保細節符合相關的法規及行業標準。 2. 制定並執行品質計畫，包括材料進場檢驗與施工過程中的品質把控，定期提交檢驗報告。 3. 協助進行空調和水機電系統的技術設計分析、規格書編寫及繪製相關技術圖紙。 4. 確保施工項目圖紙與設計規範的一致性，處理現場問題並與相關單位緊密協調。 5. 主導現場品質問題分析，提出專業化的解決方案，並有效執行改善計畫。 6. 參與空調、水機電械設備的安裝、調試與性能測試，為用戶提供技術支持。 7. 定期檢查系統安全運行情況，進行日常故障排查與維護作業，提供維修建議。 8. 負責針對團隊相關技術更新，協助舉辦內部技術教育訓練，持續提升技術團隊能力。 加入笠登工程有限公司，您將有機會運用專業技能參與重要的工程項目，共同成就高科技產業的進步。我們為員工提供良好的升遷制度、完整的教育訓練資源與住宿補助計畫。透過績效獎金及三節獎金等具吸引力的激勵措施，確保每位同仁的努力與付出能夠獲得相應的肯定。 如果您對機電品管工作充滿熱情，並希望在空調與水機電領域內實現自己的專業價值，我們誠摯邀請您加入笠登的團隊！立即投遞您的履歷，與我們攜手打造更高效的未來，期待您的加入！

我們是一家專注於半導體產業相關管線工程服務的專業公司，致力於為半導體、科技業客戶提供高品質的管路設計、安裝及維護服務。我們的服務對象涵蓋國內外科技業界，幫助客戶建構更高效、安全的管路系統。 工作內容： 1. 安裝與維護半導體或科技業建築內部及室外給水與排水系統，包括施工前的材料準備及管路規劃。 2. 負責建築物內的電線管路與用電設備的安裝與檢修，確保能源供應的穩定性。 3. 執行純水與廢水系統的管路製作、焊接及安裝，符合潔淨室環保及生產規範。 4. 使用IR紅外線機台、SM油壓機台及熱風槍等專業設備進行管路焊接和測試，保證施工品質。 5. 閱讀與解釋工程圖(P&ID, LAYOUT, PIPELINE)，並提供現場的精準管路繪圖(ISO)。 6. 定期進行管路系統的檢查與維修，確保運行過程零泄漏，並降低維修成本。 7. 參與安全和品質管理，確保所有作業符合半導體工程相關的行業標準和規範。 8. 協助上級進行施工細節的規劃及問題解決，提高工程效率。 歡迎加入我們的團隊，成為半導體產業中不可或缺的一員！如果您對管線工程有熱情並擁有扎實的相關技能，我們誠摯期待您的加入，與我們共同打造更高效、更安全的技術服務！立即投遞履歷吧！

1. 於客戶端執行設備的安裝、保養、維修及機台異常排除等。 2. 協助設備操作、參數設定，並進行試樣製程與樣品測試等。 3. 依公司安排至客戶端進行短期出差。（依公司差旅制度辦理） 4. 配合任務性質，支援國內外客戶端之服務需求。

【提供宿舍 (可依規定提出申請，享有優惠住宿費)】 1. 協助建廠之廠務無塵室、空調、冰水、機械空調系統規劃、設計、發包、監造、驗收等專案管理及相關建廠事務的執行。 2. 撰寫計劃書、專案報告、評估報告、工作簡報及相關會議記錄。 3. 系統圖面更新管理。 4. 維持空調機械系統正常運轉及改善。 5. 空調機械設備保養維護管理。 6. 其他主管交辦事宜。 ※大約2-3星期會輪一次假日值班(六或日)，時間是08:00-20:00 ※一~五上班時間09:00-18:00，工程師每周會有約一次的輪流延後2H下班 ＜以上都會依勞基法提供加班費＞

***Please apply for this position on NXP official website: https://pse.is/8ms2kr Role Purpose Lead the development and optimization of high-voltage (HV) and BCD device architectures. This role requires a deep understanding of device physics and a data-driven approach to ensure industry-leading performance and reliability for power management solutions. Key Responsibilities － Device Development: Lead the architecture design and optimization of HV devices (LDMOS, EDMOS, ESD) on 180nm to 55nm BCD nodes. － Physics Analysis: Analyze and optimize Device Physics parameters, including BV, Rdson, SOA, and reliability (HCI/NBTI). － Simulation & Modeling: Utilize TCAD for 2D/3D process and device simulations to accelerate development cycles. － Device Verification: Define verification plans and execute statistical analysis using JMP for DOE and WAT data. － Design Integration: Work within Cadence environments for layout review and test structure design. － Cross-functional Collaboration: Partner with PI and PE teams to resolve yield, reliability, and manufacturing bottlenecks. Required Qualifications － Experience: Master‘s or Ph.D. in EE, Physics, or related field with 10+ years of semiconductor industry experience. － Technical Expertise: 1. Profound knowledge of Device Architecture and Device Physics. 2. Hands-on experience in 180nm to 55nm BCD process nodes. － Tools: 1. Expertise in TCAD (Sentaurus / Silvaco). 2. Expertise in JMP for statistical data analysis. 3. Proficiency in Cadence (Layout/Virtuoso). Preferred Qualifications (Plus) － Advanced Power Devices: Experience with GaN, SiC, or IGBT development. － Silicon Photonics: Knowledge of Photonics integration and device physics. － Domain Knowledge: 1. Process Integration (PI): Understanding of mask flow and doping profiles. 2. Product Engineering (PE): Experience in CP/FT data correlation and yield enhancement. Competencies － Accountability: Strong ownership of project milestones and outcomes. － Critical Thinking: Ability to identify root causes in complex device failures. － Interpersonal Skills: Effective communication across design and foundry teams. － Data-driven: Committed to objective decision-making through rigorous data analysis.

Role Summary: The NVM Reliability team is responsible for characterizing, modeling, and enabling next-generation Non-Volatile Memory technologies, enabling new product creation company-wide. Job Responsibility: －Interface with foundries and other external suppliers of technology and IP to assess reliability margin to product applications. －Establish qualification requirements for new technology and product introduction. －Perform rigorous statistical analysis of reliability characterization data. －Enable high reliability during volume production by working with product groups to address risk areas. －Support business groups with customer requests for technical information, including reliability characterization results, risks assessments, and consultation on issues. －Communicate study conclusions and recommendations to internal and external teams. Job Qualification: －Bachelor‘s, Masters, or Doctoral degree in Electrical Engineering, Applied Physics, or equivalent, with 10 years of industry experience. －Experienced in data processing and analysis (e.g. Python, JMP, Matlab, Exensio). －Software development experience, such as familiarity with microcontroller software development (C/C++) is desired. －Interest in statistics and solid-state device fundamentals, especially as applied to emerging non-volatile memory technologies like MRAM and RRAM. －Must be curious, proactive, and detail-oriented. －Able to work in a team environment, communicate effectively in English and Mandarin, and solve problems.

The key areas of responsibility of the jobholder are: - Collaborate closely with foundries, NXP technology teams, and business lines to qualify and release advanced FinFET processes. - Provide technical leadership in semiconductor device physics, especially in FinFET architecture and behavior. - Interface with internal and external stakeholders on critical development and transfer projects. - Lead and steer projects to meet timelines and business objectives. - Make key decisions on process integration, balancing technical, logistical, and strategic factors. - Support NTI process transfers within foundries and NXP joint ventures Requirements / preferences: - Bachelor‘s or Master‘s degree in Electrical Engineering, Physics, or related field. - Minimum 10 years of experience in semiconductor device engineering, with a strong focus on advanced logic/RF devices. - Proven hands-on experience with HKMG and FinFET technologies in production or development environments. - Deep understanding of semiconductor device physics, especially HKMG and FinFET. - Strong analytical skills in yield enhancement and electrical data analysis. - Fluent in English and Mandarin. - Demonstrated leadership in development, transfer, or ramp-up projects. - Excellent communication and influencing skills. - Proactive, pragmatic, and results-driven mindset. - Experience working with foundries and leveraging external manufacturing capabilities .

***Please upload English resume onto our official platform: https://reurl.cc/qpRoqg Job Description - To work with operation/maintenance to ensure production smoothly. - To assist action confirmations with system monitors. - To work with Engineers for yield improvements from the study of stable plasma cleaning as the leading indicator. Job Qualification: - Understanding of Plasma cleaning principle for wire bonding Integrity Chip die pad/wire type/Lead-post structures - Bachelor‘s or Master‘s student in Material/Science/Electronic Engineering or related - Available to work at least 3 days/week. - Good verbal and written English communication skills - MS Office or Programming skill - Self-motivated, results oriented, willing and eager to learn, proactive attitude

1. 製程研發： 負責新製程的研發、優化與實驗，以滿足產品需求，在3D結構產品實現均勻鍍膜 2. 參數設定與驗證： 設定新設備參數並進行量產驗收，確保新製程穩定。 3. 設備改善： 進行設備改造、升級或開發。 *須出差

Please also apply through: https://nxp.wd3.myworkdayjobs.com/careers/job/Hsinchu/Tape-Out-Engineer_R-10063230 Role Overview, Responsibilities, and Qualifications The Tape Out Engineer plays a crucial role in the semiconductor design process, serving as the final checkpoint before integrated circuit designs are sent for fabrication. This position is responsible for ensuring that all physical and logical design data meet manufacturing requirements and quality standards, working closely with design, program managers, technologists, and manufacturing teams to resolve issues and optimize outcomes. Key Responsibilities 1. Coordinate and execute the tape out process for semiconductor products, ensuring timely and accurate delivery of design data to manufacturing. 2. Verify design integrity by reviewing database and documentation, and addressing any discrepancies or errors. 3. Work collaboratively with cross-functional teams, including design, technologists, program managers, and process engineering, to resolve technical issues and optimize designs for manufacturability. 4. Ensure all deliverables conform to foundry requirements. 5. Maintain detailed records of tape out procedures, revisions, and outcomes for future reference and process improvement. Qualifications 1. Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s preferred). 2. Experience with physical design tools (e.g., Cadence, Synopsys) and semiconductor manufacturing workflows. 3. Excellent attention to detail, problem-solving skills, and ability to work under tight deadlines. 4. Willingness to work with flexible working hours to support critical Tape-outs. Effective communication in English for collaborating across technical teams. This role is ideal for individuals with a passion for precision and innovation, seeking to contribute to the successful launch of leading-edge semiconductor products.