轉職熱搜工作

1.Propose design verification plan and do the execution based on IP and system HW architecture/application 2.Develop design verification environment 3.Develop required verification methodology and adopt into project 4.Develop HW emulator/FPGA platform to accelerate design verification task 5.Co-work with SW/HW engineering to valid function and shift-left SW develop 6.Debug and root cause failure with SW/HW engineering in both pre-silicon and post-silicon

1. Optimize 6G/5G modem architecture and associated hardware/software flows in aspects of system performance/power/area (PPA) to improve product competitiveness. 2. Develop architectural simulation, system-level modeling, and analysis platforms for modem baseband system performance, low-power optimization, and hard real-time (HRT) latency analysis. 3. Collaborate closely with domain architects to deliver quantitative reports based on simulation data, driving key architectural decisions. 1. 優化 6G/5G 解調架構及相關的硬體/軟體流程，提升系統效能／功耗／面積（PPA），增強產品競爭力。 2. 開發架構模擬、系統級建模與分析平台，用於評估基帶系統效能、低功耗優化與硬實時（HRT）延遲分析。 3. 與領域架構師緊密合作，根據模擬數據產出量化報告，推動關鍵架構決策。

• Lead GPU verification efforts across unit, subsystem, and full-chip levels, partnering closely with GPU architects, RTL design leads, performance engineers, modeling teams, and software/firmware teams. • Develop a deep understanding of GPU specifications and microarchitecture, including the 3D graphics pipeline, compute workloads, shader cores, memory hierarchy, cache/coherency, command processing, scheduling, and control subsystems. • Define the overall verification strategy, methodology, test architecture, milestones, and quality metrics for assigned GPU IPs and/or top-level GPU integration. • Drive creation and execution of comprehensive verification plans, ensuring traceability from architectural and RTL specifications through test implementation, functional coverage, assertions, and closure. • Lead development and maintenance of scalable SystemVerilog/UVM verification environments, including reusable agents, BFMs, scoreboards, reference models, checkers, and HW/SW co-simulation infrastructure. • Guide the team in developing directed, constrained-random, stress, error-injection, and scenario-based tests for graphics, compute, memory, and control features. • Drive functional and code coverage closure through rigorous coverage analysis, identification of verification gaps, and creation of targeted tests for corner cases and late-stage bug escapes. • Own regression health for the verification scope: establish regression strategy, monitor quality metrics, prioritize failures, coordinate triage, and drive root-cause resolution with design and architecture teams. • Review verification plans, testbench architecture, test code, coverage models, and debug approaches; provide technical mentorship and guidance to DV engineers. • Partner with performance, architecture, and design teams to develop performance-verification workloads, execute emulation/prototyping runs, analyze bottlenecks, and support performance, power, and area (PPA) optimization. • Drive efficient debug of complex RTL, testbench, firmware, and HW/SW co-simulation failures, clearly communicating root cause, impact, and resolution plans to cross-functional stakeholders. • Collaborate effectively across geographically distributed teams and communicate verification status, risks, and closure plans to project leadership.

1. Lead or support SoC architecture design, modeling, and technical feasibility studies across specific domains, including cellular modem, connectivity (Wi-Fi/Bluetooth/GNSS/UWB), performance, and power. 2. Lead or support SoC architecture development for smartphone, thin-modem, CPE/telematics, and gateway products, focusing on system performance and power considerations based on product requirements. 3. Lead or support technical feasibility studies of product requirements and collaborate with domain architects and product marketing teams to develop competitive product specifications.

Senior Technical Program Leader | USB3/USB4 Customer Issue Resolution

1.熟悉半導體封裝測試產業 2.熟悉IC設計公司產業 3.客戶拜訪開發及關係維護 4.客戶意見回饋及售後滿意度維持 (如: 顧客抱怨及問題反應處理、維持顧客對公司及業務員信賴度) 5.具備專業知識與研發設計部門溝通 6.定期與主管回報進度、績效檢討 7.其他主管交辦事項

1.依據需求規劃與建置 RF 系統，參與從概念設計到產品量產的完整開發流程。 2.測試驗證射頻電路效能，使用網路分析儀、頻譜分析儀等儀器進行RF電路測試與優化。 3.RF線路設計、阻抗匹配、PCB佈局與除錯，確保最佳射頻性能。 4.整合、測試、優化 RFIC 模組，負責無線通信、毫米波、射頻前端電路設計。 5.作為客戶技術窗口，協助技術問題溝通，參與專案會議並提供技術報告。

1. Substrate線路佈局與設計。 2. 熟悉 Cadence Allegro APD軟體操作 。 3. 負責設計產品 : 智慧型手機 (國際品牌一線大廠)、可移動穿戴式裝置 (Smart galss / Smart watch)、大尺寸液晶螢幕電視、與最先進的3C產品。

1.石英晶片加工技術分析及設計原理探討 2.石英晶片微機電技術研究與開發 3.石英晶片新產品開發及設計 4.石英元件創新技術研發 5.短期竹南及大陸出差

1. 數位設計電路開發與維護。 2. SoC系統設計電路開發與維護。 3. 數位設計與晶片系統設計技術諮詢。 4. 其它主管交辦事項。