轉職熱搜工作

1. Processor micro-architecture design 2. Cache and bus interface 3. DSP and machine learning library design 4. Simulator/modeling and architecture

Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow

【工作內容 Job Description】 1. 光模組DSP IC驗證與開發. 包含DSP IC與相關光元件 Evaluation Board (EVB) 設計、Debug 及效能最佳化。 2. 光模組參考電路設計. 包含光模組參考設計 (OSFP / QSFP-DD) Schematic 規劃、PCB Layout 指導、元件選型等硬體電路開發工作。 3. 光電特性量測與 DSP 參數調校. 光介面特性量測（包含 TDECQ, BER, Eye Diagram, Jitter, Power consumption），並與演算法 及 FW 團隊合作進行DSP參數優化。 4. 與廠商討論矽光子樣品製作 【條件要求 Requirements】 • 學歷與科系：電機、電子、光電、通信或控制等相關系所碩士或學士。 • 工作經驗：具備 2 年以上光通訊、高速介面或系統開發驗證相關經驗。 • 其他條件： 具備以下工作經驗或技能者尤佳. o 熟悉 400G / 800G/1.6T 光模組架構及測試規範。 o 具備光模組 (Optical Transceiver) 或高速 PCB 硬體設計經驗。 o 具備訊號完整性 (SI) 或電源完整性 (PI) 的理論基礎與實務經驗並熟悉高頻模擬工具, 如HFSS, ADS 等. o 熟悉高速光電測試儀器之操作, 如 DCA 高速示波器、BERT 誤碼儀、Optical Power Meter 等。 o 具備光引擎光學結構設計經驗, 包含光學模擬、設計與元件選擇等。

1. 4/5/6G modem hardware architecture and digital circuit design task 2. Define hardware architecture of a digital IP/system 3. Include Clock, Bus (AXI/APB/NOC/…), Async design, high speed IF, new IP for sub-sys design topic 4. IP and Subsys digital design and PPA optimization 5. Subsys integration from RTL to gate level including timing closure and testability 6. Design methodology and integration flow improvement

研究所以上電子、電機、資工相關系所組畢，熟悉或有興趣從事數位訊號處理(DSP)演算法，應用於Touch panel等領域。熟悉C/matlab，熟悉影像處理者尤佳，資深工程師需具三年以上工作經驗。

•重點開發技術: 系統開發、高速資料實體層(physical layer) 資料傳輸軟體開發、優化硬體效能及產品量產品質控管 •主要目標: 完成Enterprise/AI/xPU等相關產業客製化IC的軟韌體開發與系統整合，並協助客戶產品量產，有SLT的經驗 •負責新產品的系統設計與開發，確保符合公司及客戶的需求 •協助量產過程中的技術問題解決，並提供專業建議以提升生產效率與品質 •與跨部門團隊合作，確保產品從設計到量產的順利過渡 •分析並改善現有系統和流程，以提高產品質量和生產效率 •參與產品測試和驗證，確保產品符合相關標準和規範

• Lead FPGA development activities across functional prototyping, emulation, performance evaluation, and database generation flows. • Work closely with architecture, design, verification, software, firmware, and performance teams to understand system requirements and define FPGA implementation strategy. • Drive FPGA functional flow, including RTL integration, FPGA partitioning, synthesis, place-and-route, timing constraints, timing closure, bitstream generation, bring-up, and debug. • Drive FPGA performance flow to support in-house performance evaluation, workload execution, data collection, profiling, and performance database generation. • Design, implement, integrate, and optimize FPGA logic using Verilog/SystemVerilog/VHDL. • Develop and maintain FPGA prototypes and emulation platforms for system validation, software enablement, firmware development, and hardware/software debug. • Support performance analysis by enabling representative workloads, collecting runtime metrics, identifying bottlenecks, and collaborating with architecture/design teams on improvement opportunities. • Define and improve FPGA methodology, automation, build flows, regression infrastructure, and debug processes for both functional and performance use cases. • Support and integrate interfaces such as PCIe, DDR, AXI, Ethernet, SPI, I2C, UART, and other standard protocols. • Provide technical leadership, mentor engineers, coordinate cross-functional execution, and drive issue resolution across multi-site teams.

1.RTL platform design integration (clock/reset/power/bus design and architecture, MBIST, etc.) - use for FPGA and Emulator should also be considered 2.Integration quality check (RTL/SDC/Power spec signoff check)

Summary Join our Virtual Development Kit (VDK) team to build high-performance SystemC/TLM virtual platforms that enable software development and integration before hardware is available. You will develop functional IP models, integrate them into a bootable virtual SoC, and deliver test/automation that makes the platform reliable and scalable for daily software use. Key Responsibilities 1. Develop functional IP models in SystemC/TLM to enable software left-shift 2. Design clean TLM interfaces and connectivity for reusable modeling 3. Integrate IP models into a Virtual SoC (vSOC) and support system bring-up 4. Build platform-level tests and regression to validate correctness 5. Improve productivity with tooling and CI/CD automation