轉職熱搜工作

1. 主導解決客戶生產品質異常 2. 客戶端品質問題溝通協調與不良分析 (FA/8D report) 3. 推動廠內品質流程改善

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

1.協助製程良率與生產效率提升優化 2.協助生產製程規劃及工時估算 3.協助判斷設備或產品製程異常的原因及改善 4.協助專案計畫執行 5.工作需求輪班(四班二輪) ※輪班津貼另計

1. Conducting quality check procedures to ensure high-quality deliverables.​ 2. Coordinating product quality issue to provide best-fit disposition for quality event impact material.​ 3. Ensure lessons learned from prior projects are used to improve quality management process.​ 4. Customer quality communication and RMA/FA management.

1. IC封裝/晶圓凸塊技術開發與管理 2. 與封裝廠合作完成規劃之技術開發 3. 先進封裝技術開發,品質驗證與生產良率管理 4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核

1. CPU功耗分析 (設計 vs. 量測), 確保CPU功耗體質 2. CPU最大電流分析 (設計 vs. 量測), 驗證過電流保護機制確保系統穩定性 3. PMIC+PDN+CPU 功耗效率優化 1. CPU power pre-silicon vs. post-silicon correlation. Ensure CPU power quality 2. CPU max. current pre-silicon vs. post-silicon correlation. Validate max. current protection technique for system stability 3. PMIC+PDN+CPU power efficient optimization

先進封裝技術開發 1. 先進新產品導入技術開發 (新產片試產規劃, DRC/DRM檢驗, DOE及良率改善規劃, 量產區間及良率分析) 2. 熟悉先進chiplet及3DIC封裝技術開發 3. 晶圓級與面板級先進封裝結構設計