轉職熱搜工作

- 針對下一代資料中心產品，推動並導入 SoC 層級的先進功耗優化技術；與 RTL、合成與布局團隊協作，完成低功耗功能的架構規劃與導入。 - 於各設計階段（RTL → 閘級 → 佈局後）進行功耗估算與分析，提出可執行的省電建議與改善方向。 - 與 Tier-1 客戶合作制定功耗規格，並提供下一代產品的功耗估算結果與技術說明。 - 支援樣品回片後的功耗量測比對（silicon correlation）與功耗相關問題除錯（sample back / bring-up）。

加入 MediaTek「先進製程平台 DFT」團隊，你的工作直接影響 N4/N3/N2 及更先進世代 Cloud ASIC 的可靠度與良率。 - DFT 架構與插入：針對先進節點 SoC 及 chiplet/3D-IC 設計，定義並實作 Scan（full-scan、compressor）、MBIST、BSD/JTAG 架構；使用 Synopsys / Siemens (Tessent) EDA 工具執行端到端插入流程。 - ATPG 與 Advanced Fault Model：開發並優化 stuck-at、transition delay、cell-aware、path-delay 等 fault model 的 ATPG pattern；驅動 fault coverage closure 並交付 DRC-clean pattern。 - 模擬與驗證：透過 gate-level simulation（VCS/Xcelium）驗證 DFT 邏輯正確性；解決 DFT rule violation 與 coverage gap，確保 tapeout 品質。 - 後矽驗證與測試：主導 CP / FT / HTOL / HVS 各階段 DFT 工作，包含 test mode 驗證、scan chain 連通性測試、MBIST 執行與 repair 確認。 - Volume Diagnosis 與 Yield Ramp：運用 scan/MBIST diagnosis 資料分離系統性缺陷，與製程及 FA 團隊協作加速 yield learning 與技術成熟。 - RMA / DPPM 除錯：利用 DFT diagnosis 流程調查 field return，協助降低 DPPM 並防止 escape。 - 產業前沿：持續追蹤 Cloud ASIC chiplet 測試趨勢、ATE 技術進展與 EDA 新功能，主動將新觀念帶入團隊。 職務要求

1.負責 ABF Flip Chip（FC-BGA / FC-CSP）載板 Layout 設計 2.依 IC 封裝規格進行： | Bump / Pad assignment | RDL / Trace routing | Power / Ground 網路規劃 3.與客戶進行技術溝通與問題改善

高速類比SerDes電路全客製化佈局設計及自動化流程設計 Fully custom layout design for analog high-speed SerDes circuit and layout automation flow development.

1. 先進封裝BGA基板佈線與佈線實體驗證 2. 2.5D IC (CoWoS_S; CoWoS_L; CoWoS_R; EMIB) RDL 與基板佈線與佈線實體驗證 3. 與封裝設計工程師合作完成封裝設計需求與目標 4. 新封裝佈線方式評估與開發 5. 新封裝佈線輔助設計軟體評估

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=399&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 1. Support Layout production and quality verification for advanced node 2. Advanced node path finding for best speed, power and area by using layout technique. 3. Methodology development for layout optimization, productivity and quality enhancement. 4. Machine Learning/AI exploratory for layout quality and productivity enhancement. Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.

軟體：HSI（USB、PCIE、MIPI、UFS、DP、HDMI等）系統軟體（Driver／FW）－設計與驗證 硬體：HSI（USB、PCIE、MIPI、UFS、DP、HDMI等）系統硬體（PCB／PHY）－設計、驗證及PPA分析

1. Serdes PMA IP architecture planning 2. Serdes PMA IP RTL coding 3. Serdes PMA IP front-end and back-end integration 4. Co-work with PCS and MAC design team and DV team for IP verification 5. Co-work with Analog design team for PHY co-simulation 6. Co-work with Algorithm team for algorithm implementation and bit-true verification

28nm及以下先進製程(含FinFET) IO電路和ESD防護設計, 工作內容包含 (1) GPIO電路設計(包含ESD/LU防護) (2) 特殊應用IO (SD3.0/SIM card/eMMC等)電路設計(包含ESD/L防護) (3) 高速IO和特殊應用IO在事業部專案上展開和執行 - Advance node (28nm and beyond, including FetFET) IO circuitry and ESD protection design covering fields for (a) General purpose IO circuit design (with ESD/LU protection) (b) Specialty IO (SD3.0/SIM card/eMMC etc.) circuit design (with ESD/LU protection) (c) Project related implementation for high speed/specialty IO Interface - High speed IO, specialty IO circuit design, ESD protection circuit design and simulation. Work with project leader, layout, packaging and system engineers to meet design and system specifications. Work with IO library modeling, characterization teams closely for IP release.