轉職熱搜工作

1. 核心電路(SA, Driver)研發 2. 核心電路元件設計與電路模擬 3. 核心電路元件電性分析與量測 4. 核心電路佈局分析

熟悉 layout tool : Virtuoso/CustomCompiler verification : Hercules/calibre/ICV 『具工作經驗者，薪資另議』

Role Summary/Purpose: Hardware design engineer will closely work with worldwide engineers to perform engineering works for hardware testing solution of next generation semiconductor devices. The work includes requirement analysis, feasibility study, solution evaluation, task planning, project management, design execution, quality control and verification. We are working on cutting edge requirement and future technology. Responsibilities: • Provide global semiconductor interface test hardware solutions of next generation semiconductor devices for world-wide customers • Provide chip test interface HW solution engineering to compare pros and cons of different approaches and recommend best option to customers considering both performance, lead time, cost • Responsible for Testing circuits Design and super high layers PCB design for high complexity ATE device interface board correspond to various device testing, eg. Mobile application processor, High performance computer, AI, RF etc. • Responsible for scheme selection of a SUBSTRATE/MLO design in wafer testing, research for low Cost of Test scheme (considering TDE, Skip DIE, substrate stack-up) • Responsible for power integrity (PI) and signal integrity (SI) simulation at board level or system level, frequency domain or time domain to ensure HW product performance at design stage • Implement complex mechanical design/simulation, cable design, thermal evaluation by collaborating with PCB design to achieve premium quality in hardware solution according to customer device testing ultimate challenges. • Responsible for global end to end hardware project management to ensure best quality and on time delivery -Device testing requirement assessment and Feasibility study -Risk analysis and mitigation planning -Schedule planning and project management -Design execution -Regular review with global internal and external customers -Quality Control and Verification • Work closely with Global supply chain, provide solution to solve manufacture (DFM), assembly (DFA) challenges, ensure hardware products on time delivery and very high first pass rate • New technology research, new products, new materials evaluation for next generation device testing • Deliver hardware design training and seminars to customers

1.Frame layout design and generation. 2.Tapeout data preparation 3.Optical kerf and test mask layout. 4.Kerf layout library maintain. 『具工作經驗者，薪資另議』

1.依據需求規劃與建置 RF 系統，參與從概念設計到產品量產的完整開發流程。 2.測試驗證射頻電路效能，使用網路分析儀、頻譜分析儀等儀器進行RF電路測試與優化。 3.RF線路設計、阻抗匹配、PCB佈局與除錯，確保最佳射頻性能。 4.整合、測試、優化 RFIC 模組，負責無線通信、毫米波、射頻前端電路設計。 5.作為客戶技術窗口，協助技術問題溝通，參與專案會議並提供技術報告。

工作項目：IC layout 應徵條件： 1. 學士以上; 電機工程、電信工程、電子工程、通訊工程等相關科系畢業為主。 2. 具3年以上 IC layout 或相關經驗者為佳。

工作項目： 負責 Physical design(APR & IC Fully Layout)。 應徵條件： 1. 碩士以上; 電機、電子、電機與控制、自動控制、計算機、微電子相關科系畢業為主。 2. 對 IC Layout有興趣者為佳，具3-5年以上相關工作經驗者尤佳。

工作項目： 1.Responsible for physical design, including fully custom layout and Auto Placement and Routing. 2.Verification and specification achieved. 應徵條件： 1.大學以上；電機, 電機與控制, 資訊科學, 自動控制, 通訊工程, 電信, 資訊工程, 電子相關科系畢業為主。 2.具相關工作經驗者為佳。 (MD1710005、MD1810021)

工作項目： IC Fully Layout. 應徵條件： 1. 大學以上; 電機、電機與控制、電子等相關科系畢業為主。 2. 需會操作 Virtuoso XL/Mentor Calibre verification/Totem。 3. 具備 Fin-FET先進製程及 ESD、latch up、IR/EM相關知識。 4. 具 Mixed mode佈局相關經驗者尤佳。