轉職熱搜工作

工作項目： 1. High-Performance CPU/GPU Timing & Power Integrity Signoff 2. High-Performance CPU/GPU Post-Silicon Validation & Debug, Sim-to-Silicon Correlation 3. 協同開發 CPU/GPU Advanced DFT, On-Chip PVT Sensor, Performance Improvement & Power Management 等先進技術 4. 支援產品 SoC Projects，協同執行 High-Performance CPU/GPU 專案開發，導入先進 IP 及技術 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 SoC Integration & Design Flow、Frontend/Backend/DFT/Timing/IR Drop/Power Analysis EDA Tools。 3. 有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 4. 有 Chip-Level, Package & PCB Power Integrity Optimization 經驗尤佳。 5. 有On-Chip PVT Sensor 開發經驗尤佳。 6. 有Post-Silicon Validation, Debug 及 RMA 分析經驗尤佳。 7. 積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 1. CPU & GPU Backend Implementation (APR) 2. CPU/GPU Backend Flow Development, Enhancement & Automation 3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 4. 有 High Performance CPU/GPU APR經驗尤佳。 5. 個性積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 1. CPU & GPU Backend Implementation (APR) 2. CPU/GPU Backend Flow Development, Enhancement & Automation 3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 4. 有 High Performance CPU/GPU APR經驗尤佳。 5. 個性積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools. 5. Good communication and team working skills. 6. Experience in handling large scale SoC chip implementation is a plus.

1. Substrate線路佈局與設計。 2. 熟悉 Cadence Allegro APD軟體操作 。 3. 負責設計產品 : 智慧型手機 (國際品牌一線大廠)、可移動穿戴式裝置 (Smart galss / Smart watch)、大尺寸液晶螢幕電視、與最先進的3C產品。

【レイアウト設計】 DRAMメモリコアおよび周辺回路のレイアウト設計を担当します。 対象となる回路例 ・Sense Amplifier ・Wordline Driver ・I/O回路 ・周辺制御回路（アドレスデコーダー、冗長回路、タイミング制御回路、テストモード論理回路など） ・内部電源生成回路（レギュレーター、ポンプ回路） ・温度判定回路

【回路設計・シミュレーション】 DRAMメモリコアおよび周辺回路の回路設計を担当します。 対象となる回路例 ・Sense Amplifier ・Wordline Driver ・I/O回路 ・周辺制御回路（アドレスデコーダー、冗長回路、タイミング制御回路、テストモード論理回路など） ・内部電源生成回路（レギュレーター、ポンプ回路） ・温度判定回路 FinesimやHSPICEなどのツールを用いたシミュレーションを行い、スピード・消費電力などの性能を検証しながら最適な回路構成を検討します。設計者自身で実際の製品設計へ反映されるような回路構成や改善案の提案ができる点が面白さです。 【レイアウト設計・物理検証】 Virtuosoなどのツールを用いて回路図をチップレイアウトへ落とし込みます。DRC（デザインルールチェック）やLVS（回路比較検証）などの物理検証を行い、台湾本社の製造ラインで問題なく製造できる設計データを完成させます。 【評価チームとの技術連携】 試作チップの評価は台湾本社の専門チームが担当します。 設計者は評価チームとの技術的なやり取りを通じて設計意図通りに動作しているかを確認し、必要に応じて設計改善を行います。

1. IC設計流程自動化開發與維護 2. EDA軟體/iPDK安裝與管理 3. 評估EDA軟體及矽智財 (Silicon IP) 需求 4. 協助提供學界EDA軟體及矽智財使用服務並提供技術支援 5. 其他主管交辦事項

Role Summary/Purpose: Hardware design engineer will closely work with worldwide engineers to perform engineering works for hardware testing solution of next generation semiconductor devices. The work includes requirement analysis, feasibility study, solution evaluation, task planning, project management, design execution, quality control and verification. We are working on cutting edge requirement and future technology. Responsibilities: • Provide global semiconductor interface test hardware solutions of next generation semiconductor devices for world-wide customers • Provide chip test interface HW solution engineering to compare pros and cons of different approaches and recommend best option to customers considering both performance, lead time, cost • Responsible for Testing circuits Design and super high layers PCB design for high complexity ATE device interface board correspond to various device testing, eg. Mobile application processor, High performance computer, AI, RF etc. • Responsible for scheme selection of a SUBSTRATE/MLO design in wafer testing, research for low Cost of Test scheme (considering TDE, Skip DIE, substrate stack-up) • Responsible for power integrity (PI) and signal integrity (SI) simulation at board level or system level, frequency domain or time domain to ensure HW product performance at design stage • Implement complex mechanical design/simulation, cable design, thermal evaluation by collaborating with PCB design to achieve premium quality in hardware solution according to customer device testing ultimate challenges. • Responsible for global end to end hardware project management to ensure best quality and on time delivery -Device testing requirement assessment and Feasibility study -Risk analysis and mitigation planning -Schedule planning and project management -Design execution -Regular review with global internal and external customers -Quality Control and Verification • Work closely with Global supply chain, provide solution to solve manufacture (DFM), assembly (DFA) challenges, ensure hardware products on time delivery and very high first pass rate • New technology research, new products, new materials evaluation for next generation device testing • Deliver hardware design training and seminars to customers