轉職熱搜工作

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

• 負責高速SerDes的開發，包括韌體設計與演算法實現、IC功能驗證、系統效能優化以及客戶支援（熟悉架構、韌體、除錯、優化及測試相關工作） • 開發自動化驗證（使用C++、Python、C#和MATLAB） • 與類比/數位團隊合作，從原型設計到量產共同開發晶片 •協助客戶設計導入並支援量產

1. Wi-Fi 驅動程式和韌體開發設計及驗證 2. Wi-Fi 等無線晶片之跨層架構介面設計 3. 開發並取得Wi-Fi Alliance認証 4. 移植WLAN驅動程式到各Android, Linux核心和手機產品 5. 協助研發軟體新技術與新工具 6. 維護量產的產品

該工作需要和手機團隊合作研發手機BT/Thread功能，包含： 1. 開發手機專案的BT/Thread軟體協議和驅動程式 2. 設計和實作新的BT/Thread功能與規範 3. 開發並獲取BT SIG/Thread Alliance認証 4. 跨層分析問題，包含Android framework, ,Software stack, HAL, kernel, BT/Thread driver 5. 系统性地分析與優化，包含BT/Thread的性能與低功耗

1. Bus and Architecture design and RTL implementation of Smartphone chipset 2. ASIC and Smartphone SoC and mobile computing platform design. 3. System bus and mobile peripheral designs 4. SoC system performance analysis

• 規劃從silicon bring up到量產全過程的測試程式（包含 CP/FT、系統測試、DVT、HQA、相關性分析及 DPPM 降低）。 • 開發功能測試/ATPG/MBIST測試碼，涵蓋程式開發、模擬、coverage收集、機台測試程式生成以及在測試機上的驗證。 • 基於對CPU design的了解以及實驗設計, debug post-silicon DPPM, RMA問題。

Fully accountable with the team to deliver highly competitive ARM based CPU IP. Implementation skill required ranged from RTL, synthesis, DFT, Floorplan, Placement, CTS, Routing, Timing Closure, and physical verification.

1. FR-1 平台天線解決方案開發與驗證 2. 使用EM模擬軟體進行天線解決方案性能評估 3. 與跨部門團隊合作開發新MTK平台天線解決方案

1. Architecture design and RTL implementation for Smartphone and automotive chip 2. Smartphone SoC and mobile computing platform design. 3. System bus and high speed interface designs

The candidate will conduct functional verification of the RF transceiver circuit design at various stages—from individual circuit blocks to the complete system operation—using behavioral models during the design process.