轉職熱搜工作

我們正在尋找充滿熱情的產品安全工程師或研究員 (Offensive Security)，加入我們的團隊，共同鞏固我們的產品安全。這個職位將為您提供豐富的學習和成長機會，讓您在快速發展的資安領域中脫穎而出。 [工作內容] 1. 安全威脅建模: 對系統安全進行威脅建模，提出安全設計改善建議，並完善安全設計規範。 2. 漏洞分析測試: 對軟體安全進行漏洞分析、安全代碼審查，以及進行模糊/滲透測試。 3. 滲透測試開發: 發展用於漏洞發現的滲透測試方法、腳本或測試工具。 4. 前沿攻擊研究: 研究最先進的攻擊/駭客方法及趨勢，以精進各項安全測試工具及手法。 實際工作內容和範圍將根據所參與的任務而定。 [工作地點] 台北/新竹 [學習成長機會] 1. 技術多樣性: 有機會學習和接觸各式各樣的產品核心技術，擴展您的技術知識面。 2. 實戰的經驗: 與世界一流的資安研究人員合作進行安全性審查，獲得寶貴的實戰經驗。 3. 國際的視野: 參與國際資安會議，了解最新的安全趨勢和技術，提升您的專業知識。 4. 跨領域合作: 與不同技術領域的專家合作，提升您的跨領域協作能力。 加入我們，您將有機會在一個充滿挑戰和機遇的環境中成長，並為全球的產品安全做出貢獻。如果您對資安充滿熱情，並希望在這個領域中不斷進步，我們誠摯邀請您加入我們的團隊!

此職缺為數位IC設計工程師，專注於 Camera / ISP 解決方案。您將負責為多元產品（如智慧型手機、平板、車用系統及家庭娛樂設備）設計具產業競爭力的影像訊號處理器（ISP）。 工作內容： - 與 ISP 演算法工程師密切合作，設計具競爭力的 ISP / CV 硬體架構 - 交付在高效能、低功耗、最小面積之間達到最佳平衡的硬體解決方案 - 負責 RTL 設計、模擬、驗證、合成以及系統整合 - 具備創新能力，能進行 IP 設計之微架構制定與系統架構討論 - 具良好的跨部門合作、問題解決能力與技術溝通能力

1. 數位 IC 設計（RTL/電路合成/整合/驗證） 2. SoC 層級晶片設計/整合 3. DFT 相關設計/規劃/整合 4. 靜態時序分析以及收斂 5. 設計流程開發與最佳化 6. 工作地點：台北/新竹

1. TOP 設計包含：微架構、設計、模擬、測試 - DFT top, PAD top 2. TOP 和感測器的整合和模擬包含： - eFUSE - PVT 感測器和 aging 感測器 - 整合 IO 到晶片中並滿足客戶需求 3. 測試流程、環境和程式開發

- 負責資料中心相關 IP 整合，涵蓋從合成、DFT 至 GDS 交付完整流程 - 負責先進製程晶片整合，涵蓋從synthesis QC Sign-off & Tapeout

We are looking for talented engineers to join our GPU Architecture team. In this role, you will be at the forefront of defining the next generation of mobile high-performance GPUs. You will be responsible for developing a C++ based model, which serves as the primary tool for architectural exploration, bottleneck analysis, and performance projection before silicon availability. Whether you are a fresh graduate with a strong passion for computer architecture or a seasoned veteran in performance modeling, we invite you to help us push the boundaries of graphics rendering and compute efficiency.

1. USB3 Controller Maintainess/Development 2. Short term =＞ Handle the USB3 Controller for different projects and adding new features. Long term =＞ Co-work with USB4 team to co-develop the next gen USB4 controller

Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting

Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

- This position is for an SoC Architect, responsible for evaluating the technical feasibility and architectural direction of new products prior to project kickoff. - The role requires close collaboration with business teams to clarify market needs and product requirements, as well as cooperation with engineering teams to explore the competitiveness and feasibility of various SoC architecture options. - The architect will integrate cross-functional inputs to define the optimal system-on-chip design architecture, serving as the foundation for subsequent product development. - 此職缺為 SoC Architect，負責於專案啟動前進行產品的技術可行性與架構方向評估。 - 需與商務單位合作，釐清市場需求與產品規格；並與各工程團隊協作，探索不同 SoC 架構方案的優劣與競爭力，評估技術風險與可行性。 - 最終需整合跨部門意見，制定最佳化的系統晶片設計架構，作為後續產品開發的基礎。