轉職熱搜工作

我們正在重新定義晶片設計的未來，不再僅僅是設計電路，而是打造一個能夠「自我演化」的晶片設計大腦。我們正在招募具備 IC 設計與 AI 技術熱忱的工程好手，一起開創 IC 設計新時代！您將與跨領域專家攜手打造 IC Design Autonomous 的未來——運用最先進的 GAI 技術，實現從規格生成、RTL 編碼到自動化 QC 錯誤清除的完整 IC 生命週期自動化，並建立自我進化的生產力循環，讓 AI 真正落地於 IC 設計流程！ *任務描述 - 全流程自動化：設計並實作端到端的自主設計代理人 (Agentic AI) 框架，涵蓋 Spec-to-RTL 與自動化 QC 修復 - 架構演進：利用 GAI 技術進行 PPA (Power, Performance, Area) 優化，開發具備自我回饋、自我學習能力的設計閉環 - 技術領導：指導跨團隊協作，將 IC 設計流程中的自動化瓶頸，轉化為 AI 可理解並自主執行的架構 - 知識體系建構：構建領域專屬的 Knowledge Base 與 Multi-Agent 協作框架 - 研究創新：研讀最新技術、發表專利論文，將前沿研究轉化為實際應用

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification.

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification. * (If manager) Manage the design architecture team, focusing on both technological advancement and talent development.

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • End-to-End DFT Leadership: Manage comprehensive DFT activities spanning architecture definition, design implementation, verification, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications • Cross-Functional Team Coordination: Lead internal DFT teams in developing and implementing robust test solutions aligned with architectural requirements • Yield Optimization Strategy: Develop comprehensive plans for diagnosability enhancement and systematic yield improvement • Location: Hsinchu, Taipei, Singapore, USA

We are looking for a highly skilled DFT CAD and Methodology Expert to develop and deploy advanced test methodologies for next-generation data center and AI ASIC. Enhancing the efficiency and quality of our ASIC development and testing procedures. The successful candidate will work within the CAD team to innovate test solutions for complex 2.5D/3DIC, ensuring high quality and yield for advanced packaging technologies. Key Responsibilities • Methodology Development: Develop and deploy robust CAD flows for scan insertion, ATPG, pattern simulation, and Memory BIST (MBIST). • Tool Automation: Create scripts (Python, TCL, Perl) to enhance and automate DFT flows, accelerating simulation runtimes and improving quality of results (QOR). • EDA Tool Integration: Collaborate with EDA vendors to enhance tools for advanced packaging, including test verification and pattern generation. • Support & Debug: Support DFT integration teams with CAD flow issues, debug complex issues, and provide technical mentorship. • 3DIC/2.5D Expertise: Develop and implement testing strategies for chiplets and TSV-based 3D stacks. • Location: Hsinchu, Taipei, Singapore.

1、協助商場丙工櫃位規劃設計、繪製適當櫃位坪數。 2、評估櫃位一次側需求及預算費用,整合丙工櫃位界面需求, 審查櫃位裝修、機電、空調等圖說 3、櫃位設計施工說明會,櫃位場施工管理。 提供櫃位我方需求內容整合、設計材料及工法建議。 4、櫃位室裝送審與建築師配合協調溝通、資料用印。 5、專案簡報製作提案預算編列、設計施工圖面審查、材料數量核算。

1. 參加 IEEE 802.11 會議, 協助發展新的 wi-fi 規格並與將需求設計架構實現在聯發科 wi-fi chip 內 2. 設計 Wi-Fi Platform 與 STA 系統架構, 協助開發改善 performance, QoS 需求

1.協助資深工程師,硬體開發設計/測試 2.執行專案開發過程設計問題的除錯分析 3.零件料號申請、BOM表建立與修改 4.跨單位研發團隊合作開發設計、量測驗證、認證、問題協調及解決 5.協助工廠導入專案量產

1.雲端策略藍圖架構設計與落地實施: (1)設計銀行雲端基礎架構，包括計算、存儲、網路、數據平台等核心部分。 (2)規劃並部署微服務架構、容器技術（如Kubernetes）、以及無伺服器架構（Serverless）。 (3)設計支持銀行業務系統的高可用性（HA）、災難復原（DR）及自動擴展方案。 2.雲端安全與合規: (1)制定並實施雲端安全策略，確保資料隱私及應用合規性。 (2)引入多層次的安全防護措施（如IAM、加密、WAF、防火牆）。 (3)確保架構符合金融監管機構的合規要求（如ISO 27001、GDPR、本地法規）。