轉職熱搜工作

職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.

1.擔任公司資訊部門諮詢窗口，協助解決各單位資訊作業相關問題 2.配合資訊作業需要，至各單位處理連線相關作業及問題排除 3.擔任各項資訊系統維護聯絡廠商、及測試工作 4.協助機房檢查與紀錄 5.監視器調閱 協助 6.投影機筆電 架設 7.行政事務交辦事項 8.基本電腦更換處理

FairWind are looking for qualified installation technicians for wind farm work on the western side of Taiwan. This is a fantastic opportunity to continue your career in wind energy and increase your skills with assisting in the installation and possible commissioning of projects. Your strong safety ethic and knowledge of teamwork will be highly regarded in this position. As the successful candidate you will have the following qualifications; • Full AT or Test for Dead (TfD) AT • GWO – BST & BTT • WTSR Core • MMI • TOS • SIT This work will start in early August and continue for up to six weeks with the potential to extend. If you have the experience and enthusiasm to provide the best works possible, FairWind want you on our team. Please apply now and one of our professional recruitment team will make contact with you. Please send your CV to: jnicholas@fairwind.com

1. 確認軟體程式的目的與功能，進行程序開發及測試，並撰寫軟體程式技術白皮書 2. 負責網站開發工作 3. 熟悉HTML5/CSS3/Javascript /jQuery技術。 4. 熟悉 RWD Frameworks。 5.了解前端框架（Vue ）。 6. 熟悉Restful API協定，配合後端工程師規劃API架構。 7. 能獨立作業處理問題。

參與系統分析與設計、系統程式開發、對應系統操作問題及異常排除。 (1)設計並打造直覺且高效的前端介面，滿足專案需求。 (2)參與系統設計，確保效能優越且易於擴展。 (3)持續維護並優化現有系統，確保其穩定與高效。 (4)進行代碼審查，提升代碼品質並保持其可讀性與安全性。 (5)協助進行SIT與UAT測試，確保系統功能正常運作並持續提升性能 (6)具備BPM 知識者佳。 (7)具備Javascript 知識者佳。 (8)具備C# 知識者佳。

1.電路板開發、 產品電路設計、產品測試除錯 2.與試產人員溝通，協助順利產出設計之電子產品，並於生產中指導確保零件組裝過程與設計相同 3.攝影機組裝.測試.QC

1.協助推動公司內部 AI 應用導入，盤點各部門工作流程與需求，評估適合導入生成式 AI、資料分析或流程自動化的應用場景。 2.與跨部門業務及資訊團隊合作，進行需求訪談、流程梳理、PoC 規劃與導入成效追蹤。 3.協助導入 ChatGPT、GPT、RAG 知識庫、AI Agent、Chatbot、文件摘要、報表解讀、客服輔助與內部流程自動化等應用。 4.協助評估 Codex、AI coding assistant、Dify、LibreChat、MCP 或其他 AI 協作工具，支援資訊處開發、測試、文件整理與內部系統串接。 5.協助評估 AI 工具、LLM 服務、SaaS 平台及外部供應商方案，進行需求確認、成本效益、資安與個資風險初步評估。 6.運用 AI 輔助撰寫需求文件、測試紀錄、操作流程、教育訓練教材與導入成果報告，並協助建立 AI 使用規範、Prompt 範本與人工覆核流程。 7.主管交辦事項

1.協助百貨專案推展事項，專案項目涵蓋POS銷售系統、餐飲系統、支付金流，於專案期間確認專案執行項目、向協力廠商提出系統需求、共同規劃系統機能(系統規格書)、負責系統測試、系統管理文件製作、教育訓練安排、系統導入及支援、系統上線後問題受理及排除。 2.本職務為專案管理與執行，非系統程式開發，須配合值班安排。 3.主管臨時交辦事項。