轉職熱搜工作

1. Java Web相關程式設計與開發。 2. Java測試與維護經驗，邏輯能力強具獨立作業處理問題。 3. 規劃軟體模組設計，研發軟體新技術與新的解決方案。 溫馨提醒：只有經過台郡授權的人員才能處理您的個人簡歷，台郡亦將遵守相關法規與政策，保護您的個人資料。投遞簡歷視同您同意台郡收集您的個人資訊。

先進材料及製程開發暨廠建需求 菁英徵召 (化學專才) 1.實驗及材料特性測試 2.製程參數優化及流程標準化 3.參與新產品導入與會議討論 4.設備評估及設置 5.新產品導入製作及樣品進度掌控及各製程串聯 6.新產品新設計檢視 溫馨提醒：只有經過台郡授權的人員才能處理您的個人簡歷，台郡亦將遵守相關法規與政策，保護您的個人資料。投遞簡歷視同您同意台郡收集您的個人資訊。

Role Summary: We are seeking a Principal Product Engineer to support advanced optical product development, NPI, manufacturing transfer, production ramp, and sustaining engineering in Taiwan. This is a senior individual contributor role requiring deep hands-on experience in fiber optics, optical module manufacturing, process integration, yield improvement, and cross-functional execution with engineering, operations, quality, supply chain, and contract manufacturing teams. The ideal candidate will serve as a technical lead for optical product engineering in Taiwan, helping drive products from development builds through qualification, pilot production, and high-volume manufacturing. Key Responsibilities: • Lead product engineering execution for optical products from prototype builds through qualification, production release, and sustaining support. • Support NPI planning, engineering builds, manufacturing readiness, test readiness, process transfer, and ramp execution. • Drive technical issue resolution across optical assembly, fiber attach, process integration, module test, final test, reliability, and customer quality. • Work closely with design engineering, optical engineering, packaging, test, reliability, operations, quality, and supply chain teams. • Partner with contract manufacturers and suppliers to resolve yield, quality, process, material, and production ramp issues. • Lead data-driven yield improvement using production data, failure pareto analysis, root-cause investigation, corrective action, and process optimization. • Support development and release of optical assembly and fiber attach processes, including process flows, control plans, inspection criteria, process windows, and manufacturing release criteria. • Provide technical leadership for product characterization, margin analysis, failure analysis, reliability learning, and production excursion response. • Help define manufacturing specifications, test limits, outgoing quality controls, and product-level production metrics. • Support customer or supplier technical escalations related to product quality, manufacturing performance, or reliability.

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and testing skills will be put to good use. Successful handling with many external teams from pre-silicon phase cross to post-silicon on advance silicon and assembly process. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • Product test planning capability: Manage comprehensive post-silicon flow optimization, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications.

We are looking for a DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality. Key Responsibilities • Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. • Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. • Perform ATPG, fault simulation, and coverage analysis. • Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. • Lead silicon bring-up and debug of test features; conduct failure and yield analysis. • Work with product teams to facilitate pattern generation, validation, and DPPM improvement.

## 關於團隊 (About the Team) MediaTek IoT BU 的 Linux Platform Team 負責 MediaTek Genio 平台的 Linux 系統軟體與 distribution 開發。我們長期與合作夥伴、開源社群及 upstream maintainer 協作，打造可維護、可擴充，並符合標準 Linux 生態系的 Yocto、Ubuntu 與 Debian 解決方案。 我們正在尋找一位 Senior AI Engineer，主導 MediaTek ONNX NeronEP（ONNX Execution Provider）的開發與優化。這個職位將聚焦於 ONNX Runtime 框架整合、NPU 加速、客戶模型效能分析，以及 Debian/Ubuntu 生態系整合，協助 MediaTek AI 解決方案更容易被客戶、開發者與合作夥伴採用。 在這個角色中，你將參與真實 Edge AI 產品落地，面對 robotics、drone，以及未來 GenAI on edge 等應用場景。你也將有機會參與 ONNX Runtime upstream 與標準 Linux distribution 整合，讓你的工作成果進入更廣泛的開發者生態系，並直接影響全球客戶的 AI 產品開發體驗。 ## 你將負責的工作 (What You‘ll Be Doing) - 主導 MediaTek ONNX NeronEP（Execution Provider）的開發、維護與效能優化，並以 NPU 作為主要加速後端。 - 與內部 runtime、driver、compiler、platform 團隊，以及外部合作夥伴協作，推動 NeronEP upstream 到 ONNX Runtime 官方專案，並維持與新版 ONNX Runtime 的相容性。 - 分析客戶 ONNX 模型，定位效能瓶頸與功能缺口，判斷問題來自 runtime、driver、kernel、硬體加速器，或模型本身的設計與優化空間，並提出具體改善建議。 - 開發模型優化、效能分析、debug 工具與 reference applications，降低客戶導入 MediaTek AI 解決方案的門檻。 - 推動相關 AI 工具鏈以 Debian/Ubuntu package 形式提供，支援標準 Linux distribution 的整合、部署與長期維護。 - 支援客戶 AI 專案從 PoC 到產品化過程中的技術問題，重點包含 debug、效能分析、模型優化與 deployment 建議。 ## 職位資訊 (Position Info) - 工作地點：台北，on-site - 職位性質：Individual Contributor，專注於技術深度與跨團隊技術推進，不負責 line management。此角色將需要密切協調內部團隊與外部合作夥伴，共同推動開發、整合與產品落地。 - 所屬部門：MediaTek IoT BU — Linux Platform Team

1 Develop the Timing/IR signoff criterion for leading process node and 3DIC. 2 Maintain the Timing/IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing/IR violation 3 Develop new Timing/IR signoff methodology to be applied during chip synthesis/APR/STA/IR . 4 SPICE correlation for new timing/IR signoff criterion 5 Regression test for every signoff methodology by STA violation/slack analysis, IR results 6 Post-silicon data analysis for silicon-proven timing/IR signoff criterion

加入 MediaTek「先進製程平台 DFT」團隊，你的工作直接影響 N4/N3/N2 及更先進世代 Cloud ASIC 的可靠度與良率。 - DFT 架構與插入：針對先進節點 SoC 及 chiplet/3D-IC 設計，定義並實作 Scan（full-scan、compressor）、MBIST、BSD/JTAG 架構；使用 Synopsys / Siemens (Tessent) EDA 工具執行端到端插入流程。 - ATPG 與 Advanced Fault Model：開發並優化 stuck-at、transition delay、cell-aware、path-delay 等 fault model 的 ATPG pattern；驅動 fault coverage closure 並交付 DRC-clean pattern。 - 模擬與驗證：透過 gate-level simulation（VCS/Xcelium）驗證 DFT 邏輯正確性；解決 DFT rule violation 與 coverage gap，確保 tapeout 品質。 - 後矽驗證與測試：主導 CP / FT / HTOL / HVS 各階段 DFT 工作，包含 test mode 驗證、scan chain 連通性測試、MBIST 執行與 repair 確認。 - Volume Diagnosis 與 Yield Ramp：運用 scan/MBIST diagnosis 資料分離系統性缺陷，與製程及 FA 團隊協作加速 yield learning 與技術成熟。 - RMA / DPPM 除錯：利用 DFT diagnosis 流程調查 field return，協助降低 DPPM 並防止 escape。 - 產業前沿：持續追蹤 Cloud ASIC chiplet 測試趨勢、ATE 技術進展與 EDA 新功能，主動將新觀念帶入團隊。 職務要求

- Collaborate with architects and cross-functional teams to understand GPU specs and define verification strategies. - Develop SystemVerilog/UVM test frameworks and co-simulation environments; verify GPU logic at unit, subsystem, and top levels. - Create and execute verification test plans, focusing on functional coverage. - Generate random and directed test sequences; maintain testbench, scoreboard, BFMs, and regression. - Perform RTL and coverage analysis; optimize test scenarios and address bug escapes. - Support performance verification, emulation, data collection, debugging, and PPA improvements. - Conduct formal verification.

Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting