測試工程師|1111轉職專區
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  • 5G Radio System Design and Application Engineer

    面議(經常性薪資達4萬元或以上) 新竹市東區 2~3年工作經驗
    1. 進行射頻系統性能驗證工作,確保測試結果符合測試規範需求。 2. 與演算法及軟體部門合作開發與PA相關的省電技術。 3. 使用DPD技術改善PA的線性度與效率。 4. 支持重要客戶完成工廠校準時間的優化工作。 5. 撰寫高品質的技術文檔,並交給客戶支援單位以執行客戶支持。
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  • HSI (High-Speed Interface) PHY System Design Validation Engineer

    面議(經常性薪資達4萬元或以上) 新竹市東區 工作經歷不拘
    -規劃並執行高速介面(如 PCIe, USB, DP, UFS, CSI, UCIe)IP PHY 驗證。 -建立並維護測試平台,進行 System 與 Electrical 測試。 -使用 Scope, BERT, LA, Signal Analyzer 等儀器進行 Signal Integrity 與 Compliance Test。 -分析測試結果,協助 DE 及 SW 團隊解決問題。 -設計並開發硬體 PCB 評估板,支援系統驗證。
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  • <Automotive>Software Engineer for System Power Modeling

    面議(經常性薪資達4萬元或以上) 新竹市東區 5~6年工作經驗
    1. 開發用於模擬手機/平板/車用SOC功率消耗的平台 2. 協助IP, SOC與軟體團隊,維護用於功耗分析的資料庫,開發相關工具以輔助跨團隊的資訊整合 3. 優化系統效能,輔佐系統功耗相關決策的進行
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  • Stress/Thermal simulation engineer

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 2~3年工作經驗
    1. Package related structure stress analysis including warpage, material study. 2. Package and board level stress modeling for TCT, drop and vibration. 3. IC and package thermal analysis, modeling and characterization 4. Chip-Package-PCB thermal co-simulation and design. 5. System level thermal simulation 6. System level stress simulation
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  • Package and Chip thermal/stress simulation engineer

    面議(經常性薪資達4萬元或以上) 40000元 新竹市東區 4~5年工作經驗
    1. Package related structure stress analysis including warpage, material study. 2. Package and board level stress modeling for TCT, drop and vibration. 3. IC and package thermal analysis, modeling and characterization 4. Chip-Package-PCB thermal co-simulation and design. 5. System level thermal simulation 6. System level stress simulation
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  • DFT/MBIST engineer for advanced process node & package technology

    面議(經常性薪資達4萬元或以上) 新竹市東區 4~5年工作經驗
    1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip
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  • Analog/Mixed-Signal Design Verification Methodology Development Engineer

    面議(經常性薪資達4萬元或以上) 新竹市東區 10~11年工作經驗
    Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products. • Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. • Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. • Document on new flows and processes for AMS DV. • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA
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  • 115年度暑期實習_軟韌體開發_SW engineering & automation Product security (台北)

    月薪 29500~48000元 台北市內湖區 工作經歷不拘
    (請留意:為加快面試安排時間,僅限定投遞5個職缺)我們在找這樣的你:對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣;勇於表達意見,以團隊成功為目標,面對困難不輕易放棄,總是在想更好的做法,擁有創新及不斷學習的精神。聯發科技邀請您,與全球最頂尖的菁英一同合作,彼此激盪最新的創意與解法,共同挑戰每一個不可能。
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  • 115年度暑期實習_軟韌體開發_SW engineering & automation Product security (新竹)

    月薪 29500~48000元 新竹市東區 工作經歷不拘
    (請留意:為加快面試安排時間,僅限定投遞5個職缺)我們在找這樣的你:對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣;勇於表達意見,以團隊成功為目標,面對困難不輕易放棄,總是在想更好的做法,擁有創新及不斷學習的精神。聯發科技邀請您,與全球最頂尖的菁英一同合作,彼此激盪最新的創意與解法,共同挑戰每一個不可能。
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  • 115年度校招/研發替代役/應屆預聘正職_軟韌體開發_SW engineering and automation Product security (新竹)

    面議(經常性薪資達4萬元或以上) 新竹市東區 工作經歷不拘
    (請留意:為加快面試安排時間,2026校招僅限定投遞5個職缺)我們在找這樣的你: 資工/資管/電子/電機/電信/通訊/電控相關研究所背景,對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣的2026年應屆畢業生。 勇於表達意見,以團隊成功為目標,面對困難不輕易放棄,總是在想更好的做法,擁有創新及不斷學習的精神。 聯發科技邀請您,與全球最頂尖的菁英一同合作,彼此激盪最新的創意與解法,共同挑戰每一個不可能。
    展開