轉職熱搜工作

1.應用建築機電知識及經驗，協助解決其他相關問題 2.編撰各項計畫書 3.訂定檢驗停留點，辦理抽查施工作業及抽驗材料設備，並填具紀錄表且簽認(含照片) 4.抽查施工廠商放樣、施工基準測量及各項測量之成果。 5.巡查及督導現場安全衛生、環境保護...等工作 6.提送計畫書、預定進度表、施工圖、施工日誌、材料送審、估驗計價、竣工結算驗收等相關資料審查及工作事宜 7.機電設備測試及試運轉 8.填寫工作日報表(每日填寫) 9.廠商送審資料進度控管 10.公司主管交辦事項及勞務契約書規定工作內容 資格： 1.具有公共工程品質管理人員證照

1.BT新材料、新機台評估測試 2.層間導通孔之雷射技術測試開發、新機台評估測試 3.特殊結構流程評估開發 4.新產品導入評估開發

1.自動化設備機構設計開發，具獨立設計開發能力。 2.機台驗證測試與修改。 3.圖面繪製及相關技術文件產出。 4.配合團隊產品優化與技術支援。

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=250&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. As a Cybersecurity Engineer, you will perform incident investigation, mitigation, and prevention (SOC), and develop or implement security controls. You will collect world-wide intelligence to build-up detection rules and perform application security enforcement and penetration-test to reduce AP vulnerability. Responsibilities: 1. Perform cybersecurity incident investigation, mitigation and prevention (Security Operation Center). 2. Develop or implement the security controls to assist in detection, prevention and analysis of security threats. 3. Collect the world-wide cybersecurity intelligence (hacking activity, TTP, IOCs) and build-up the detection rules to strengthen the visibility and detection rate. 4. Perform application security enforcement and penetration-test for reducing AP vulnerability. Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.

***本職缺將安排完整的教育訓練*** 一、講座教育訓練(系統構成、機台構成、作業SOP) 二、實機教育訓練(操作教育、設備校正教育、品質檢查教育、電源盤調整教育) 【工作內容】 1.台積電F22廠 。 2. 執行自動化設備之相關安裝校正。 3. 維持廠內自動化系統之正常運作。 4. 進行自動化設備維護、保養、異常排除。 5.自動化設備耗材更換 6.無相關工作經驗 〝可〝 團隊裡有完善的新人教育訓練 【其他條件】 1.個性需積極、細心、負責、配合度高。 2.需有無塵室工作且著全套無塵衣經驗。 3.可配合設備導入常駐客戶端工作。 4.需配合常態性出差。

1.電路板開發、 產品電路設計、產品測試除錯，軔體編輯 2.樣品製作實驗、樣品承認、建BOM 3.據產品設計人員進行PCB Layout 4.進行PCB佈局和 layout工作 5.協助硬體工程師完成PCB板及軔體調試 6.開發案文件管理 7.管理儀器與設備. 8.工程樣本製作

公司期待透過完善的專案歷練與海外跨國舞台，使同仁能獨立操作大型專案，未來逐步晉升為資深系統工程師、系統工程師主管職、部門主管及海外專案核心幹部。 【團隊成長與多元學習福利】 ★ 跨領域成長：我們非常注重團隊發展，提供多元化的學習環境，不侷限於單一技術的學習，讓您的職涯更具廣度與深度！ ★ 證照與進修：公司大力鼓勵每位員工在職進修，全力支持您考取相關專業技術證照，並提供實質的升遷與職涯加分。 ★ 國際化舞台：具備完善的海外發展機制，若工作表現優異，未來將有機會外派至國外工作、參與跨國專案，大幅拓展您的國際視野！ ★ 我們非常期望認真、負責、樂於學習且勇於挑戰自我的人才加入團隊，與公司一同並肩成長！ 本職務為公司工程技術與專案管理之中堅骨幹。透過一線實務的主導、專案進度的精準控管以及跨領域技術的整合，負責帶領工程團隊並指導助理工程師，確保各項專案在品質、安全與時程上完美達標，相關經驗兩年以上。 【日常工作職掌】 專案進度與現場管理 工程技術與圖面作業 設備組裝與安裝測試 行政庶務與工安推行 工安政策與出差配合 ＞＞＞專案出差支援：依專案地點配合出差與合宜之調配安排（需不定期支援台南與高雄廠區往返，或依專案需求配合跨區廠區支援）。

主要為發電機併聯控制盤、水情收集盤 誠徵 : 電機工程師 / 儲備幹部 1.控制盤規劃與設計Cad繪圖 2.PLC程式及人機程式撰寫 3.從事控制盤之功能廠驗測試 4.從事現場併聯控制盤與發電機控制迴路的連接與測試 5.配合發電機人員做併聯測試 6.從事控制盤之維修、售服 7.高低壓配電盤設計

職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).