轉職熱搜工作

職責要求 1. 集團材料技術管理 2. 集團材料工程應用與精進專案 3. 材料與塗佈製程效益提升 4. 新材料開發與驗證 任職資格 1.碩士/研究生，化學、應用化學、化工相關科系相關科系畢尤佳，相關工作經驗5年以上 2.具高分子化學與應用、聚合物合成技術與開發、微膠囊化技術經驗尤佳 3.具英文讀寫能力 4.熟悉Word,Excel,PowerPoint

1. Supplier Management: Manage key substrate suppliers and conduct rigorous QCDST evaluations to ensure alignment with MediaTek‘s standards. 2. Capacity & Supply Planning: Monitor substrate market dynamics (focusing on ABF) to secure long-term capacity reservations and strategic allocations. 3. Risk Mitigation: Track upstream raw materials (e.g., CCL, T-glass fiber) and cultivate 360-degree relationships with key vendors to prevent supply disruptions. 4. Cost Optimization: Drive cost-reduction targets through in-depth cost structure analysis, process optimization, and quarterly/annual price negotiations. 5. NPI & Technology Alignment: Partner with Package Design and R&D during the NPI phase to evaluate supplier technology roadmaps and mass-production feasibility. 6. Cross-functional Issue Resolution: Collaborate internally to expedite solutions for material shortages, quality excursions, and urgent order modifications. 1. 供應商管理： 管理主要的基板供應商，並進行嚴格的 QCDST（品質、成本、交期、服務、技術）評估，以確保其符合聯發科的標準。 2. 產能與供應規劃： 監控基板市場動態（特別是ABF基板），以確保長期產能預留以及策略性分配。 3. 風險控管： 追蹤上游原材料（如CCL、T玻纖），並與主要供應商建立全方位的夥伴關係，以預防供應中斷。 4. 成本優化： 透過深入的成本結構分析、流程優化，以及季度／年度價格談判，推動達成成本降低目標。 5. 新品導入與技術協同： 在新品導入（NPI）階段，與封裝設計及研發部門合作，評估供應商的技術藍圖與量產可行性。 6. 跨部門問題解決： 內部協作，快速解決原物料短缺、品質異常與緊急訂單變更等問題。

1. 2.5D/3.5D package technology development​ 2. SoC/Memory heterogeneous integration package development​ 3. Package technology integration, NPI and MP​ 4. Project management​

1.產品測試確保品質、打樣生產 2.於實驗室工作研發開發生物科技產品如:化妝品.清潔品 3.化學反應槽機台操作、儀器分析與化學檢測 4.紀錄所有試驗過程，無論失敗與否，供後人參考 5.規劃製程並協助製程異常改善及追蹤、製品品質管制 6.化學材料研究、評估分析、測試及選擇，可請實驗化驗人員協助分析材料，物質粹取等 7.將成功之化學配方寫下，包括化學量劑加入順序，量劑等 8.主管交付配合事項 9.熟悉ERP操作

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=550&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. RD Integration starts with the definitions, including transistor architecture and design building blocks, of a new technology node. Then, a manufacturable process flow is developed for evaluations and further improvements. The tasks may involve multidiscipline technical knowledge bases and project management skills. The job will require a lot of collaborations, so frequent communication should be expected. Test structure are designed in order to evaluate the manufacturing processes. Test vehicles will be built, and real chips will be validated through yield, performance, and reliability learning cycles. The goal is to deliver an optimized semiconductor technology that will meet the required chip performance, power, area-per-function, costs, and time-to-market (PPACt) for our customers. Responsibilities: Apply advanced computational models to predict performance, optimize structure and doping profile, and provide improvement directions in nano-scaled device technologies. Develop and apply finite element method (FEM) modelling, including but not limited to stress simulations, computational fluid-dynamics, thermal conductivity simulations and electromagnetic wave simulations, for both macroscopic (tool/wafer) and microscopic (discrete device) structures. Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16521&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. We are seeking a highly motivated and talented R&D Engineer to join our team in developing advanced IC packaging technologies. This position offers an exciting opportunity to work on cutting-edge solutions, such as CoWoS (Chip-on-Wafer-on-Substrate), Fan-Out Wafer Level Packaging (FOWLP), and 3DIC (Three-Dimensional Integrated Circuits). The ideal candidate will have strong technical expertise and a passion for innovation in semiconductor packaging design and analysis. Join us in shaping the future of advanced IC packaging technologies and contributing to groundbreaking innovations in the semiconductor industry. This role provides a unique opportunity to work in a dynamic environment, solve challenging engineering problems, and make a meaningful impact on next-generation packaging solutions. Responsibilities: 1. Conduct risk assessments and provide mitigation plans for IC packages through simulation and experiment, interpreting experimental data and simulation to provide insights into material selection and design improvements. 2. Practice FEM and DOE in problem solving and path finding particularly on packaging. Conduct mechanical or thermal simulations using finite element analysis (FEA) techniques to evaluate and optimize packaging performance, and analyze stress, deformation, and heat dissipation characteristics to ensure reliability and efficiency of packaging designs. 3. Continuously improve simulation methodology, refine material modeling, and enhance script automation capabilities. Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.

1. Automotive Packaging development, New product introduction, Mass production, Supplier management.​ 2. Develop and evaluate the advanced IC Package technology.​ 3. Collaborate with the assembly subcontractors to complete the technology development.​ 4. Qualification and yield improvement for the advanced IC Packages.​ 5. Audit subcontractors.

1. Develop systematic methodology to alleviate design challenges, including FIP development, synthesis, DFT, physical implementation, sign-off, process what-if assessment, system performance evaluation, in advanced nodes or package. 2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies. 3. Explore new circuit architecture, EDA features and define improvement direction from MTK product requirements.

先進封裝技術開發 1. 先進新產品導入技術開發 (新產片試產規劃, DRC/DRM檢驗, DOE及良率改善規劃, 量產區間及良率分析) 2. 熟悉先進chiplet及3DIC封裝技術開發 3. 晶圓級與面板級先進封裝結構設計