轉職熱搜工作

- 架構與規格設計： 定義與設計射頻積體電路 (RFIC) 系統架構，並制定先進通訊解決方案的詳細技術規格。 - 校準與控制開發： 開發並驗證射頻校準演算法與射頻系統控制流程，以優化收發器在各種環境下的效能表現。 - 通訊系統與數位訊號處理： 設計無線通訊系統，並針對射頻性能優化與非理想特性補償，開發專用的數位訊號處理 (DSP) 演算法。 - Architecture & Specification: Define and design RFIC system architectures and detailed technical specifications for advanced connectivity solutions. - Calibration & Control: Develop and verify RF calibration algorithms and RF system control flows to optimize transceiver performance across various conditions. - Communication System & DSP: Design wireless communication systems and implement digital signal processing (DSP) algorithms specifically tailored for RF performance enhancement and impairment compensation.

1. Develop Ethernet MAC for HPC networking applications. 2. Work closely with architecture, verification and physical teams from specification to implementation.

1. 5G modem 架與數位電路設計 2. CLK, 測試, Reset相關設計與規劃 3. 低功耗設計 4. 系統整合 RTL 到 Gate level, 含STA

1. Work on 2~4nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. Develop Die-to-die and UCIe digital IP for HPC SOC. 2. Integration of D2D controller and PHY to timing closure and DFT. 3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation. 4. Work closely with multiple teams such as mixed mode designers and Firmware engineers.

1. Work with design teams to do performance sign off in pre-silicon stage 2. ESL platform and simulation/emulation technology development. 3. Model development (includes behavior modeling/ cycle approximate modeling)

1. Serdes/High speed interface related PHYD IP architecture planning. 2. Serdes/High speed interface related PHYD IP RTL coding. 3. Serdes/High speed interface related PHYD IP front-end and back-end integration. 4. Co-work with MAC design team and DV team for IP verification. 5. Co-work with Analog design team for PHY co-simulation.

負責設計並優化數位相機及影像信號處理領域之IC，與演算法團隊協作，共同開發領先業界的影像處理解決方案，應用於智慧型手機、平板、車用及家庭娛樂等高成長市場。 工作職責 : - 與演算法工程師協作，設計高效能影像信號處理（ISP）/電腦視覺（CV）電路 - 提供優化硬體方案，達成IC設計「黃金三角」：最小矽面積、極低功耗、最佳影像品質 - 負責RTL設計、模擬、驗證、邏輯合成與整合流程 - 參與專案系統架構與技術研討，提出創新設計方案 - 支援產品跨部門整合及技術溝通