轉職熱搜工作

1.執行IQC、PQC、FQC、OQC之品質檢驗與記錄/報表 2.產品物性、化性檢測與記錄/報表 3.協助品質異常處理事宜 4.協助品檢數據資料分析前置作業及記錄表單歸檔 5.臨時交辦作業 職位價值敘述: 確保產品品質符合標準。

【工作內容】 1、專案規劃與執行 ●制定專案計畫，包含時程、資源與費用管理。 ●管理 APP、行銷平台、支付工具（行動支付、刷卡機）、票券系統等多元專案進度。 ●規劃並推動新功能開發與系統優化，確保交付成果符合品質與時效。 2、需求溝通與協調 ●與內外部團隊（工程師、業務、需求單位等）合作，梳理需求並確認開發可行性。 ●持續追蹤開發進度，確保交付內容符合需求並具可執行性。 3、系統維運與異常處理 ●監控系統運作，建立異常追蹤與處理機制。 ●協調技術團隊及外部廠商，確保異常能即時排除。 4、費用與合約管理 ●負責專案相關之費用議價、請款流程與廠商合約協調。 ●掌握專案費用及付款進度，確保資源運用效率。 5、專案驗收與整理 ●撰寫專案追蹤與成果文件，涵蓋需求統整、測試腳本與操作指引。 ●建立並維護系統操作說明，並提供需求單位疑難排解與支援。

1.產品尺寸線上巡檢 2.車床設備保養與維護 3.基本故障排除作業 4.產品檢測與記錄 5.桌上型車床簡易加工(倒角) 6.協助清理銅鐵鋁等廢料 7.送料機材料整補 8.廠區協助清潔維護 9.有意願與興趣可培訓成為CNC操作工程師，表現優良予以升遷機會

1. 環保系統的操作檢查及保養作業 2. 配合環保及職安法令執行各項紀錄及申報作業 3. 環保系統及作業環境等各項監控及檢測作業 4. 工作計劃之執行及檢討 5. 環保系統的改善 6. 配合各環保單位稽查作業 7. 職安衛相關議題及作業環境的工安改善 8. 配合及協助主管指派之相關專案作業 9. 因應部門需求之各項請購、驗收、及應付作業 10. 配合上級主管交辦事項 職位價值敘述: 1. 確保公司運作符合各項環保法規。 2. 協助改善工廠作業環境及降低工安風險。 3. 持續朝節能減碳及ESG相關要求之目標執行,創造公司競爭力。

職責要求 1.辦理電力系統相關工程技術，需熟悉電驛保護協調、電力相關標準，並執行型態管理，以確保設備設計功能正常、維持營運安全。 2.協辦電力系統升級、置換等相關工程之技術研擬及現場管理作業，包含招標及技術文件撰稿、現勘、監工、測試、點移交作業等。 3.系統性設備異常營運與維修技術支援，需與採購、設備介面單位及契約承商等協作，執行專案工程履約管理作業，確保工程契約符合安全準則。 4.協助評量施工與測試作業風險，規範風險減輕需求。 5.分責承辦部門工程合約之設計審查、意見彙整與澄清、介面與排程協調、施工與測試監察進度管控與彙報等合約執行作業項目。 6.依公司政策，辦理與其他機關單位之技術協助與相關業務。 任職資格 1.大學以上，電機電子工程相關系所，英文中上可溝通及閱讀英文文件 2.具高考電機工程技師尤佳 3.熟悉工程專案管理作業與一般採購合約流程與管理 4.熟悉軌道供電系統相關子系統包括：變電系統、輸電系統、電力監控系統、配電系統及道旁機電系統等

職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.

職責要求 • app 開發維護架構設計，iOS / Android 平台 • 與同仁溝通協調去設計和交付功能 • 重構來優化效能與改善程式品質 • 撰寫程式文件 • 持續增加測試 • 撰寫 Script 以取代 routine task 任職資格 • 熟悉Cocos2d-x • 有主動學習並獨立解決問題的能力 • 三年以上軟體工程師之經驗 • 熟悉版本控制軟體 Git, Git Flow • 有透過撰寫測試(Unit test)來改善程式碼品質的經驗 • 擅長溝通協調，會使用不同的方式（如文件，畫圖，敘事）幫助溝通更順暢 加分項目： • 熟悉 Cocos2d-x 與 iOS, Android native 平台串接 API 的流程 • 熟悉 Cocostudio • 熟悉與網路服務之間的整合，Restful API 和 Websocket • iOS, Android native App開發經驗 • 有伺服器相關開發經驗 • 多人即時連線遊戲設計經驗 • 瞭解 DevOps 或服務部署方法和流程，使用過雲端服務經驗，如 AWS, Google cloud • 了解基本 Javascript 語法 5.與後端工程師配合，串接 API，完成產品開發＜br/＞ 6.模組化前端組件，建立前端開發架構，提高前端開發的效率＜br/＞ 7.對前端相關領域技術保持持續關注，用合理的技術方案解決問題＜br/＞