轉職熱搜工作

對於DFT晶片測試有興趣者，特別是 Automotive low DPPM DFT 以及 RISC-V DFT 領域， 負責開發與實行DFT流程，以降低測試成本、提高產品品質為目的 As a member of DFT engineering team, the candidate will develop methodologies and implement DFT for pre/post-silicon DFT flow and contribute to Automotive/RISC-V product test quality. Work with senior engineers across disciplines (DE, IMP, PE, TE) to meet low cost and high quality testing

1. 從事實體設計化，設計方法開發及簽核工作 2. 執行布局，時序規劃，擺置及繞線，確保時序收斂及實體驗證。 3. 需參與團隊, 合作完成專案。 4. 須具備程式技巧以完成工作。 5. 使用到的工具有: ICC2, Innovus, Formality/LEC, PrimeTime, Calibre 等等。

1. Processor core, cache and peripheral verification 2. Verification flow and methodology 3. Advanced tool and verification technology survey

Fully accountable with the team to deliver highly competitive ARM based CPU IP. Implementation skill required ranged from RTL, synthesis, DFT, Floorplan, Placement, CTS, Routing, Timing Closure, and physical verification.

1. AI ISP 硬體架構設計 2. 系統power 與 bandwidth 設計 3. 相機規格制訂 4. ISP 硬體系統規格驗證規劃 5. 車用安全規劃

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

The candidate will design, supervise layout, help characterize transceiver front-end circuits for WiFi and Bluetooth production.

1. Design and RTL implementation of SoC debug modules 2. Integration and verification of debug components (e.g., trace, monitor, access port) 3. Debug signal capture, trace, and analysis for SoC platforms 4. Support SoC debug flow and issue localization 5. Collaborate with cross-functional teams to optimize debug performance 6. Documentation and test specification for SoC debug features 7. Location: Taipei/Hsinchu

1.數位電路設計 2.多媒體架構與電路設計 3.多媒體系統整合 1.Digital IC Design 2.Multimedia Architecture and Design 3.Multimedia System Integration