轉職熱搜工作

Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

此職缺為數位IC設計工程師，專注於 Camera / ISP 解決方案。您將負責為多元產品（如智慧型手機、平板、車用系統及家庭娛樂設備）設計具產業競爭力的影像訊號處理器（ISP）。 工作內容： - 與 ISP 演算法工程師密切合作，設計具競爭力的 ISP / CV 硬體架構 - 交付在高效能、低功耗、最小面積之間達到最佳平衡的硬體解決方案 - 負責 RTL 設計、模擬、驗證、合成以及系統整合 - 具備創新能力，能進行 IP 設計之微架構制定與系統架構討論 - 具良好的跨部門合作、問題解決能力與技術溝通能力

- 負責資料中心相關 IP 整合，涵蓋從合成、DFT 至 GDS 交付完整流程 - 負責先進製程晶片整合，涵蓋從synthesis QC Sign-off & Tapeout

1. USB3 Controller Maintainess/Development 2. Short term =＞ Handle the USB3 Controller for different projects and adding new features. Long term =＞ Co-work with USB4 team to co-develop the next gen USB4 controller

We are looking for talented engineers to join our GPU Architecture team. In this role, you will be at the forefront of defining the next generation of mobile high-performance GPUs. You will be responsible for developing a C++ based model, which serves as the primary tool for architectural exploration, bottleneck analysis, and performance projection before silicon availability. Whether you are a fresh graduate with a strong passion for computer architecture or a seasoned veteran in performance modeling, we invite you to help us push the boundaries of graphics rendering and compute efficiency.

- Collaborate with architects and cross-functional teams to understand GPU specs and define verification strategies. - Develop SystemVerilog/UVM test frameworks and co-simulation environments; verify GPU logic at unit, subsystem, and top levels. - Create and execute verification test plans, focusing on functional coverage. - Generate random and directed test sequences; maintain testbench, scoreboard, BFMs, and regression. - Perform RTL and coverage analysis; optimize test scenarios and address bug escapes. - Support performance verification, emulation, data collection, debugging, and PPA improvements. - Conduct formal verification.

Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting

1. TOP 設計包含：微架構、設計、模擬、測試 - DFT top, PAD top 2. TOP 和感測器的整合和模擬包含： - eFUSE - PVT 感測器和 aging 感測器 - 整合 IO 到晶片中並滿足客戶需求 3. 測試流程、環境和程式開發

- This position is for an SoC Architect, responsible for evaluating the technical feasibility and architectural direction of new products prior to project kickoff. - The role requires close collaboration with business teams to clarify market needs and product requirements, as well as cooperation with engineering teams to explore the competitiveness and feasibility of various SoC architecture options. - The architect will integrate cross-functional inputs to define the optimal system-on-chip design architecture, serving as the foundation for subsequent product development. - 此職缺為 SoC Architect，負責於專案啟動前進行產品的技術可行性與架構方向評估。 - 需與商務單位合作，釐清市場需求與產品規格；並與各工程團隊協作，探索不同 SoC 架構方案的優劣與競爭力，評估技術風險與可行性。 - 最終需整合跨部門意見，制定最佳化的系統晶片設計架構，作為後續產品開發的基礎。

In a flexible and supportive environment, one of your major responsibilities is to push the state of the art of learning theory. Furthermore, through collaboration with worldwide colleagues, you will have the rare opportunity to apply advanced Deep Learning theories to novel application areas such as AI-designed IC and General Intelligence Conversation. We welcome all ML/DL backgrounds, including computer vision, speech and NLP, and robotics.