轉職熱搜工作

The candidate will design, supervise layout, help characterize transceiver front-end circuits for WiFi and Bluetooth production.

* Define and optimize SOC hardware architecture and associated software flows in aspects of system performance/power/area to improve MediaTek‘s product competitiveness. * Develop simulation and analysis platforms for performance/power/area analysis. * Work Loction : HsinChu, Taipei

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

1. Interpret customers’ functional safety requirements 2. Derive functional and technical safety concepts from functional safety requirements 3. Develop and review the safety IP design 4. Communicate and coordinate safety designs with IP teams 5. Perform system safety analysis (ex: FMEDA)

AI Model development, system level modeling and HW/SW system level bottleneck analysis

1. Develop 3.5D methodology from RTL to GDS and Package 2. Coordinate Thermal and PI/SI team to deal with high power design 3. Execute the project at different phases

1) 移植及建置Linux/Android/Yocto系統與相關軟體至既有SoC平台 2) 負責IC模組驗證，平台開機問題分析與解決 3) 建構及優化Booting流程 4) 系統分析與效能改善 5) 記憶體管理優化任務

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip

使用者體驗指標定義和品質保證，使用者體驗驗證工程師。 負責定義旗艦/高端/中端/低端的使用者體驗指標，預估未來用戶體驗發展，確保產品具競爭力。分析競品與客戶對接討論，開發測試手法與測試用例。 有Android phone 使用者體驗/功耗性能 設計或測試經驗，尤其有手機大廠相關測試規劃經驗者，將優先考慮。