轉職熱搜工作

★工作時間： 月休八天，上班時段面談，平均每日工時 8–9 小時。 ★工作內容： 負責門店變臉演出，帶來驚喜並營造沉浸氛圍； 規劃與執行多樣表演，全面提升顧客用餐體驗； 結合節慶與市場需求，創新設計專屬演出內容； 維護現場秩序與安全，靈活處理突發狀況挑戰； 協助主管交辦事項，學習及支援各部門崗位業務。 ★應徵條件： 喜歡與人互動交流，具親和力與表達力； 對音樂及節奏敏感，能掌握表演氛圍與情境； 無變臉經驗亦可，需有學習企圖心並願接受完整培訓； 期望長期穩定投入，短期工讀或僅打工者請勿投遞； 錄取後需提供餐飲從業人員體檢報告，保障健康與專業。 ★薪資： 入職保底月薪42,000 元。前三個月享另全勤獎金 2,000 元/月 → 合計 44,000 元 考核通過後：提供專屬訂製變臉服，依表演場次與表現，平均薪資 45,000–65,000 元。 參與門店其他業務可領協助薪資，另依績效表現享分紅獎金。 ★福利： 全日免費供膳、員工用餐專屬折扣； 多元獎金制度，年度小年夜及春酒歡聚； 春節團圓假期，定期健康檢查守護身心； 主管另享補助：教育津貼、租屋津貼、孝親津貼； 表現優異者可申請海外派駐，開拓國際職涯舞台！

1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. CPU system design, Power, performance and Area analysis 2. MCUSYS u-Architecture design 3. AMBA System bus architecture and integration

1.負責 ASIC Memory IP Driver 軟體開發與 IC驗證環境 2.熟悉軟/韌體、優化、IC驗證 及 除錯 等工作項目 3.執行 IC bring up 與韌體系統整合的工作

1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency 2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip 3. Architectural modeling, validation, definition and documentation 4. Driving implementation across design, verification, firmware and software teams

1. AI 處理器系統架構/微架構設計 2. AI 處理器系統 BUS 與 memory, power/clock/reset 控制電路及其周邊相關電路設計 3. 車用安全性相關設計

Design the 5G and next-generation modem processor with cost effective, high speed, and low power hardware performance. This position will develop the modem processor that optimized for modem system. Co-work closely with software and system architecture colleague to analysis the sweet point of system performance and low power. In this position, you will push the physical performance to next level and co-work with place-and-route (PAR) team resolving the bottleneck of speed and power.

1. Work on 3~7nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution