轉職熱搜工作

1.自動化設備機構設計開發，具獨立設計開發能力。 2.機台驗證測試與修改。 3.圖面繪製及相關技術文件產出。 4.配合團隊產品優化與技術支援。

1.廣告活動規劃、協調及促銷宣傳、商圈市場調查 2.店舖行政工作管理與帳務處理 3.接受顧客詢問或主動提供諮商建議給顧客 4.向顧客說明產品的性質、特徵、品質與價格

職責要求 •Design TX/RX, analog front-end, serializers/deserializers, high-speed level shifters, predrivers/drivers, and termination/impedance calibration blocks. •Equalization: Feed-Forward Equalization (FFE), DFE, CTLE and related adaptation/control loops. •Clocking support for links (e.g., CDR interactions, low-jitter clock generation/distribution as needed by PHY). •SI analysis and creation/validation of IBIS/IBIS-AMI models; channel characterization (insertion loss, return loss, crosstalk) and eye diagram margin assessment. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Support interface integration and sign-off: PPA optimization, reliability checks (e.g., EM/IR, aging/overstress), and timing closure collaboration. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Reference generation: bandgap, bias circuits, reference voltages/currents; high-accuracy, low-noise design techniques. •Low offset / low-noise voltage regulators (LDO) and stability/compensation networks; PSRR and transient response optimization. •Voltage and power monitoring circuits: droop detection, voltage detectors, PowerGood and POR generation, analog sensing, and housekeeping blocks. •Power-management components, linear and/or switching-adjacent blocks, charge pumps, as applicable to the SoC/PHY environment. •Design/support ADC/DAC blocks and associated analog support circuits (sampling, references, amplifiers/comparators, clocking). •Voltage and temperature sensor design and characterization. Bandgap and PTAT-based temperature sensing; process corner detection circuits. Sensor readout, digitization, and calibration techniques. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

職責要求 •Design high-speed TX/RX analog buffer circuits for LPDDR6 memory interfaces, including output drivers, input receivers, level shifters, termination, impedance calibration, biasing, and reference circuits. •Define and implement programmable drive strength, slew-rate control, and on-die termination schemes to meet LPDDR6 electrical and timing requirements. •Translate system and interface specifications into detailed transistor-level circuit architectures and design specifications. •Own end-to-end block/IP delivery, including architecture studies, schematic design, pre-layout simulation, post-layout extraction, and sign-off. •Build and maintain verification test benches; validate performance across PVT corners, mismatch/Monte Carlo, aging, and post-extraction parasitics. •Analyze high-speed performance metrics such as eye margin, jitter, timing skew, voltage noise sensitivity, and simultaneous switching effects. •Work closely with layout engineers to provide floorplanning guidance, review critical layouts, and ensure robust matching, isolation, and parasitic control. •Support interface integration and sign-off, including power, performance, area (PPA) optimization and reliability checks (e.g., EM/IR, overstress, aging). •Support testchip and product silicon bring-up, characterization, and correlation with simulation results; drive root-cause analysis and ECOs as needed. •Collaborate effectively with digital design, verification, layout, package, SI/PI, product, and test teams. 任職資格 •BS or MS in Electrical/Electronics Engineering or related field. •Typically 5+ years of relevant experience in analog/mixed-signal IC design, with emphasis on high-speed I/O or memory interface circuits. •Strong fundamentals in CMOS device operation, analog circuit design, feedback and stability, noise/jitter analysis, and deep-submicron effects. •Hands-on experience designing high-speed TX/RX buffers, termination and impedance calibration circuits, and voltage-domain level shifters. •Proficiency with industry-standard design tools, typically including Cadence Virtuoso, Spectre/ADE or HSPICE, and post-layout extraction flows. •Ability to clearly communicate design intent, document trade-offs, and drive results in a cross-functional environment. •Basic written English proficiency required. Candidates must be able to read and write emails in simple English to communicate effectively with non-Mandarin-speaking colleagues. Preferred / Nice-to-Have Experience •Experience with memory or high-speed interface protocols such as LPDDR, DDR, HBM, or similar interfaces. •Experience with post-layout sign-off, EM/IR analysis, and reliability-aware analog design. •Familiarity with signal integrity concepts, channel effects, and interaction between I/O circuits and package/channel parasitics. •Experience supporting silicon validation, ATE characterization, and simulation-to-silicon correlation. •Scripting or automation experience using Python, SKILL, Verilog-A, or similar for simulation regression and result analysis.

1.幫助師父處理外場安裝所需材料及工具準備工作; 2.跟隨師父學習專業的技能，並且處理廚具安裝最基礎的工作; 3.內場廚具組裝學習

一、【財務管理與策略規劃】 1. 財務管理擬定與實施：擬定公司整體財務策略與中長期財務目標，支援執行長與創辦人進行經營決策分析，協助企業進行財務規劃與資產配置，協助公司達成經營目標。 2. 資金管理：資金流通預測與運用，包括未來半年度現金流量預測、資金調度控制。 3. 財務規劃：編製年度預算、未來半年度資金收支預估，並進行實際與預算差異分析表，提供部門滾動式調整。編製年度及滾動式預算，並持續追蹤與檢視執行成效，分析營運效率。 二、【帳務與報表處理】 1. 財務報表編製與審核：編製現金流量表，確保數據正確與合規性。監督日常財務銀行作業與帳務正確性並審閱付款資金報表。 2. 帳務制度建立與內控制度：規劃與優化流程與制度，防止財務舞弊。 3. 帳目審核與憑證查核：財務作業管理，定期抽查憑證、核對帳務。 4. 公司預算管理，資金流財務預測：現金資金控管，確保公司運營現金流穩健及資金使用效率提高，預估未來三個月帳目現金流財務預測。 三、【稅務與法遵管理】 1. 稅務規劃與法遵管理：確保公司依法申報各類稅務（營所稅、營業稅等），並進行財務面節稅規劃。協助規劃公司整體稅務策略並制定節稅方案申報，妥善因應稅務稽核與查核優化稅務結構，降低企業稅務風險。 2. 法規遵循：配合政府法規與審計要求（如IFRS、公司法等），避免違法風險。 3. 稽核與查帳協助：主導年度稅務稽核或內部稽核工作，確保審計順利進行。 四、【跨部門協調與溝通】 1. 與高層管理溝通：提供財務建議、財報分析，協助決策。 2. 跨部門協調：與營運、設計、行銷等部門合作，確保預算執行與資源分配合宜。 3. 銀行與外部關係管理：維持與銀行、會計師事務所、稅務顧問等外部單位之良好互動。 五、【主管交辦事項】 1. 執行主管交辦之其他事項：臨時交辦／專案支援。 六、【內控制度與風險管理】 1. 建立與持續優化內部控制制度，評估潛在風險(評估公司運營資金壓力測試)，制定避險及應變方案。 七、【跨部門協作與策略支持】 與行銷、業務、採購等部門合作，提供財務觀點，支持跨部門策略與營運決策。 八、【對外關係與資本運作】 維繫銀行、會計師等外部合作夥伴關係，作為公司財務面主要窗口對應發言人。 九、【協助ERP系統設置】 定期因應公司型態變化，更新設置鼎新ERP系統(COSMOS ERP)新交易流程導入與設定