轉職熱搜工作

1. Package related structure stress analysis including warpage, material study. 2. Package and board level stress modeling for TCT, drop and vibration. 3. IC and package thermal analysis, modeling and characterization 4. Chip-Package-PCB thermal co-simulation and design. 5. System level thermal simulation 6. System level stress simulation

1. Responsible for high-speed UCIE development, including architecture definition, verification, and customer support (familiar with architecture, firmware, debugging, optimization, and testing tasks). 2. Define architecture and specifications through simulations. ( Matlab ) 3. Develop test automation. 4. Collaborate with the team to establish system prototypes and optimize performance. 5. Achieve product integration for clients and support mass production.

• 規劃從silicon bring up到量產全過程的測試程式（包含 CP/FT、系統測試、DVT、HQA、相關性分析及 DPPM 降低）。 • 開發功能測試/ATPG/MBIST測試碼，涵蓋程式開發、模擬、coverage收集、機台測試程式生成以及在測試機上的驗證。 • 基於對CPU design的了解以及實驗設計, debug post-silicon DPPM, RMA問題。

1. SOC platform 架構與RTL implementation 2. 負責 IP/子模組之 RTL 整合，組成 SoC (System-on-Chip) 或子系統的頂層設計。 3. 依據設計規格，串接不同來源或平台的 RTL，確保各模組間介面相容與功能正確。 4. 撰寫與維護整合 RTL 的頂層模組、配置腳本及連結測試環境。 5. 針對整合後的設計進行功能模擬、靜態時序分析（STA）、Lint、CDC 及等驗證工作，並協助 debug。 6. 與軟硬體、驗證、後端設計等團隊密切合作，確保整合流程順利與產品交付時程。 7. 編寫設計文件及協助設計交付相關事務。

1. Design and RTL implementation of SoC debug modules 2. Integration and verification of debug components (e.g., trace, monitor, access port) 3. Debug signal capture, trace, and analysis for SoC platforms 4. BUS topology and debug mechanism circuit design 5. Support SoC debug flow and issue localization 6. Collaborate with cross-functional teams to optimize debug performance 7. Documentation and test specification for SoC debug features

1.CP/FT testing flow development & verification 2.Product manufacturing yield analysis & improvement

1. Develop and implement EVB procurement and business strategies. 2. Coordinate with R&D/Engineering to confirm EVB specs, quantities, uses, budget, and delivery schedule. 3. Source suitable EVB suppliers and manage second source options. 4. Issue RFQs, compare quotations, and assist supplier selection. 5. Support technical reviews and sample testing. 6. Confirm procurement terms, place orders, and track delivery. 7. Manage goods receipt, handle issues, and provide after-sales support. 8. Establish and monitor key KPIs, resolve issues promptly, and implement process controls. 9. Maintain supplier evaluation and procurement procedures; conduct audits and acceptances. 1. 制定並執行EVB採購及營運策略。 2. 與研發/工程部門協調，確認EVB規格、數量、用途、預算及交期。 3. 探尋合適的EVB供應商，並管理第二來源選項。 4. 發送詢價單，比較報價，協助供應商選擇。 5. 支援技術審查及樣品測試。 6. 確認採購條件，下單並追蹤交貨進度。 7. 管理收貨驗收、處理異常問題，並提供售後服務。 8. 建立及監控關鍵KPI，及時解決問題，並實施流程管控。 9. 維護供應商評估及採購流程，執行稽核與驗收流程。

分析及優化手機 5G TestBed 平台的效能，包括以下項目 1. 整合與移植不同 Linux 平台 (Ex. Ubuntu, Cent, RedHat, ...) 2. 整合與應用 Intel/AMD CPU Accelerator API (Ex. Intel Core i9 9/10/12th AVX/TBB/MKL; AMD...) 3. 分析與調校系統整體效能 (Ex. Linux Kernel, Process, Thread, Peripheral(Ethernet/PCIe/...) Driver, ...)

We are looking for a DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality. Key Responsibilities • Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. • Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. • Perform ATPG, fault simulation, and coverage analysis. • Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. • Lead silicon bring-up and debug of test features; conduct failure and yield analysis. • Work with product teams to facilitate pattern generation, validation, and DPPM improvement.