轉職熱搜工作

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=343&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibility: 1. Design CMOS Image Sensor (CIS) & depth sensor related test chips for process development 2. Design CIS or non-CIS test lines or test chips for process monitoring and improvement 3. Data acquisition and analysis: CIS key performance indices and random noises characterization

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=475&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Organization Introduction: We are power grid design and sign-off team for digital design inside TSMC. The mission is to develop power grid design and co-optimize with semiconductor process in advanced technology nodes for most updated commercial design contents (CPU, GPU, SoC, etc.) Our power grid designs are references for worldwide 1st Tier design houses. Responsibilities: 1. Develop power grid structure for most updated commercial design contents (CPU, GPU, SoC, etc.) and check IR/EM (Electron-Migration) performance. 2. Provide design solutions for IR/EM and routing optimization. 3. Co-work with process R&D for process tuning to achieve better PDN (Power Delivery Network) design. 4. Support TSMC advanced process node test chip PDN sign-off checks, including PDN quality check, static/dynamic IR sign-off, and EM sign-off for successful chip tape-out. 5. Provide guidance and suggestion to PnR (Place and Route) designer on PDN issue fixing.

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16573&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. 智慧製造工程師為創造晶圓產出最大化，滿足客戶交期，為公司帶來營收；身為工廠的第一線管理者，需掌握生產流程，藉由良好且精準派工提升機台生產效率，帶領技術員團隊確保製造流程順暢運行並達成每日的產能目標。 As a global semiconductor technology leader, TSMC is seeking an Intelligent Manufacturing Engineer to join our team. Our commitment to driving manufacturing excellence has led us to integrate artificial intelligence, machine learning, expert systems, and advanced algorithms to build up an intelligent manufacturing environment. Join TSMC, we are the most advanced technology team and connect with the world, as we head towards an unlimited future. We look forward to you joining us! You will be assigned to one of the following five roles according to your interest, experiences, and technical background. Responsibilities: 1. MFG Intelligent Manufacturing Engineer 2. CIM Intelligent Manufacturing Engineer 3. Data Analyst & Data Scientist 4. AMHS (Automated Material Handling System) Engineer 5. PIDS/WAT (Wafer Acceptance Test) Engineer 6. PIDS/NTO (New TapeOut) Engineer 7. Quality Management Engineer

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16565&source=1111&tags=AO+2026_1111 Description : R&D Engineers will be part of a grand joint-force working on advanced technologies, including but not limited to exploratory research in advanced device architecture, market-oriented design IP enablement, device and process integration for manufacturability, package-level interconnect solutions, and novel material/equipment/process evaluations. Responsibilities: 1. Research & Pathfinding (1) New material and new process pathfinding to enable new device architecture with integration. (2) New tool pathfinding for new materials to enable the next nodes. (3) Design, execute and analyze experiments to meet R&D engineering specifications. (4) Process stability & manufacturability improvement for yield and reliability qualification. (5) Process/tool transfer to development R&D or volume manufacturing (Fab). (6) Highly motivated individuals with a strong technical background and teamwork skills. 2. Integration (1) Technology definition: design rules, design-technology co-optimization, logic/memory IP evaluations, etc. (2) Technology development infrastructure: productivity enhancement, product inspection methodology, mask-making, and test flow, etc. (3) New test vehicle establishment and validation: improvement of device yield and reliability (learning cycles). Improve yield and reduce defects by quantifying defect attributes using programming skills and developing effective detection methodologies. (4) Customer design enablement: SPICE Modeling and IP qualifications. 3. Module (1) Develop advanced processes, materials, tools, models, and computational methodologies for leading edge technologies. (2) Deliver manufacturable, stable, cost-effective technologies with device performance improvement for yield and reliability qualification. (3) Transfer process and tool to high volume manufacturing fab. 4. R&D Process Center (1) PE: Advanced module process development and baseline sustaining. (2) EE: Handle advanced equipment at R&D stage. Install, warm up, sustain and troubleshooting solve with new technology equipment. (3) MFG: Oversee the daily operations of IC foundry to ensure that all profiling operations, workflow, and customer reports are consistent with agreed upon service operations.

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16566&source=1111&tags=AO+2026_1111 Description : At the beginning of new module research, IC design engineers and R&D engineers would closely cooperate with customers. Once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time. At TSMC, you will have the opportunity to work with the most advanced module technologies, provide solutions to partners in the global IC design ecosystem, and ensure competitiveness in power, performance, and area. Responsibilities: 1. Physical Designer The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps which include floor plan, PNR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. The candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements. 2. Standard Cell Engineer (1) Pathfinding of library characterization for leading edge tech nodes. (2) Support industrial standard library kits generation and QC. (3) In-house library generation flow and/or utility development. (4) RC parasitic extraction analysis and APR related analysis. 3. Layout Engineer (1) IC layout for advanced technology (Std. cell/Memory/AMS/IO). (2) Layout structure development for new technology. (3) Pathfinding for new technology development. (4) Customer engagement and layout support. (5) Design and technology co-optimization (DTCO). (6) AI and automation for layout and physical design. 4. System and Chip Design Solutions Development Please refer to the Link: https://careers.tsmc.com/zh_TW/careers/JobDetail?jobId=516 5. FE design & DFT (1) Test chips development for advanced nodes, including physical design (APR), logic synthesis and DFT (Scan insertion + ATPG). (2) Design flow development for test chips design, which requires the programming skills, Tcl, Python, C-shell scripting etc. (3) Technology benchmarking for PPA evaluation of the advanced nodes. (4) DTCO (Design & Technology Co-Optimization) pathfinding and development. 6. SRAM Engineer (1) SRAM design in advanced nodes for mobile, high-performance computing, IoT, automotive applications. (2) RRAM/MRAM, emerging memory development. (3) In memory computing research and development. 7. Design Flow/Methodology (1) Advanced technology process design kits (PDK) and tech files (DRC, LVS, RC, etc.) development and technical support. (2) Advanced technology design development flow development and technical support. (3) Automation program development to support design kits and flow development productivity/quality.

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16576&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: TSMC‘s advanced packaging process is an efficient and high-density packaging technology that mainly targets the demand for high-performance semiconductor components, including microprocessors, graphics processors, artificial intelligence chips, etc. This technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration. TSMC‘s packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution. TSMC‘s advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields. TSMC‘s advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device (logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production.

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16588&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. We are looking for an experienced IT Specialist to support the digital transformation of our corporate finance systems. This role requires a hands-on technologist with solid software development skills and a strong understanding of treasury operations and AI/ML integration. Key responsibilities include: 1. Design, develop and enhance the IT infrastructure within Finance Division. 2. Work closely with finance teams to understand needs and deliver technical solutions. 3. Develop and maintain code in Java, JavaScript, and SQL environments. 4. Integrate AI/ML models into finance systems for predictive analytics and automation. 5. Ensure system security, scalability, and compliance with financial regulations.

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址： https://careers.tsmc.com/careers/JobDetail?jobId=446&source=1111 台積公司成立於1987年，率先開創了專業積體電路製造服務之商業模式，自此成為世界領先的專業積體電路製造服務公司。台積公司以領先業界的製程技術及設計解決方案組合支援其客戶及夥伴生態系統的蓬勃發展，以此釋放全球半導體產業的創新。身為全球的企業公民，台積公司的營運範圍遍及亞洲、歐洲及北美，致力成為企業社會責任的行動者。2023年，台積公司提供最廣泛的先進製程、特殊製程及先進封裝等288種製程技術，為528個客戶生產1萬1,895種不同產品。台積公司企業總部位於台灣新竹。 進一步資訊請至台積公司網站 https://www.tsmc.com.tw 查詢。 說明: 1. 在製程部門，協助工程師處理線上事務，包含產品異常處置與機台異常復歸(與設備工程師協調合作)，追蹤與執行工程師交接事項 2. 在量測部門，協助工程師維護量測程式，量測資料異常確認，量測機台異常復歸(與設備工程師協調合作)，追蹤與執行工程師交接事項 3. 在檢測部門，操作電子顯微鏡拍照並針對拍攝的缺陷照片進行分類，檢測機台異常復歸(與設備工程師協調合作)，追蹤與執行工程師交接事項 4. 採四班二輪制：工作兩天，休息兩天 5. 須輪班：依部門而異，3~5個月夜班、3~5個月日班 6. 班別工作區間(含休息時間)：日班-7:20AM~7:20PM；夜班-7:20PM~翌日7:20AM 7. 日班總月薪約32,000 元；夜班總月薪約 43,000 元；另享有分紅獎金，平均年薪達75 萬元以上

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=6371&source=1111 台積公司成立於1987年，率先開創了專業積體電路製造服務之商業模式，自此成為世界領先的專業積體電路製造服務公司。台積公司以領先業界的製程技術及設計解決方案組合支援其客戶及夥伴生態系統的蓬勃發展，以此釋放全球半導體產業的創新。身為全球的企業公民，台積公司的營運範圍遍及亞洲、歐洲及北美，致力成為企業社會責任的行動者。2023年，台積公司提供最廣泛的先進製程、特殊製程及先進封裝等288種製程技術，為528個客戶生產1萬1,895種不同產品。台積公司企業總部位於台灣新竹。 進一步資訊請至台積公司網站 https://www.tsmc.com.tw 查詢。 說明: 1. 在製程部門，協助工程師處理線上事務，包含產品異常處置與機台異常復歸（與設備工程師協調合作），追蹤與執行工程師交接事項 2. 在量測部門，協助工程師維護量測程式，量測資料異常確認，量測機台異常復歸（與設備工程師協調合作），追蹤與執行工程師交接事項 3. 在檢測部門，操作電子顯微鏡拍照並針對拍攝的缺陷照片進行分類，檢測機台異常復歸（與設備工程師協調合作），追蹤與執行工程師交接事項 4. 採四班二輪制：工作兩天，休息兩天 5. 須輪班：依部門而異，3~5個月夜班、3~5個月日班 6. 班別工作區間（含休息時間）：日班-7:20AM~7:20PM；夜班-7:20PM~翌日7:20AM 7. 日班總月薪約32,000 元；夜班總月薪約43,000 元；另享有分紅獎金，平均年薪達75萬元以上

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=4670&source=1111 台積公司成立於1987年，率先開創了專業積體電路製造服務之商業模式，自此成為世界領先的專業積體電路製造服務公司。台積公司以領先業界的製程技術及設計解決方案組合支援其客戶及夥伴生態系統的蓬勃發展，以此釋放全球半導體產業的創新。身為全球的企業公民，台積公司的營運範圍遍及亞洲、歐洲及北美，致力成為企業社會責任的行動者。2023年，台積公司提供最廣泛的先進製程、特殊製程及先進封裝等288種製程技術，為528個客戶生產1萬1,895種不同產品。台積公司企業總部位於台灣新竹。 進一步資訊請至台積公司網站 https://www.tsmc.com.tw 查詢。 說明: 1. 在製程部門，協助工程師處理線上事務，包含產品異常處置與機台異常復歸(與設備工程師協調合作)，追蹤與執行工程師交接事項 2. 在量測部門，協助工程師維護量測程式，量測資料異常確認，量測機台異常復歸(與設備工程師協調合作)，追蹤與執行工程師交接事項 3. 在檢測部門，操作電子顯微鏡拍照並針對拍攝的缺陷照片進行分類，檢測機台異常復歸(與設備工程師協調合作)，追蹤與執行工程師交接事項 4. 採四班二輪制：工作兩天，休息兩天 5. 須輪班：依部門而異，3~5個月夜班、3~5個月日班 6. 班別工作區間(含休息時間)：日班-7:20AM~7:20PM；夜班-7:20PM~翌日7:20AM 7. 日班總月薪約32,000 元；夜班總月薪約 43,000 元；另享有分紅獎金，平均年薪達75萬元以上