轉職熱搜工作
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Quality and Reliability Engineer
面議(經常性薪資達4萬元或以上) 40000元 新竹市 工作經歷不拘【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=352&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 1. Reliability data test, analysis,and monitor. 2. New hotspot pattern and test methodology study for WAT(Wafer Acceptance Test) monitoring. 3. FAB process change management for reliability risk assessment management. 4. Circuit reliability and product reliability. 5. Customer service on reliability.展開 -
A10 RD Device Engineer
面議(經常性薪資達4萬元或以上) 40000元 新竹市 工作經歷不拘【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=302&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. RD Integration starts with the definitions, including transistor architecture and design building blocks, of a new technology node. Then, a manufacturable process flow is developed for evaluations and further improvements. The tasks may involve multidiscipline technical knowledge bases and project management skills. The job will require a lot of collaborations, so frequent communication should be expected. Test structure are designed in order to evaluate the manufacturing processes. Test vehicles will be built, and real chips will be validated through yield, performance, and reliability learning cycles. The goal is to deliver an optimized semiconductor technology that will meet the required chip performance, power, area-per-function, costs, and time-to-market (PPACt) for our customers. Responsibilities: 1. 10 Å CMOS platform technology development. 2. With focus on transistor characterization, design, targeting, and performance step-up. 3. Lot handling & on-duty (night shift and weekend) rotation.展開 -
A10 RD Engineer (Coding)
面議(經常性薪資達4萬元或以上) 40000元 新竹市 工作經歷不拘【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=328&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. RD Integration starts with the definitions, including transistor architecture and design building blocks, of a new technology node. Then, a manufacturable process flow is developed for evaluations and further improvements. The tasks may involve multidiscipline technical knowledge bases and project management skills. The job will require a lot of collaborations, so frequent communication should be expected. Test structure are designed in order to evaluate the manufacturing processes. Test vehicles will be built, and real chips will be validated through yield, performance, and reliability learning cycles. The goal is to deliver an optimized semiconductor technology that will meet the required chip performance, power, area-per-function, costs, and time-to-market (PPACt) for our customers. Responsibilities: 1. Develop AI rule generator and QC pattern generator for complex design rule. 2. Automation for Design Rule Quality Check flow by python. 3. Automation for Design Rule Quality Check flow by excel VBA. 4. Advance technology and design co-optimization for manufacturing & PPAC.展開 -
IT Security Engineer
面議(經常性薪資達4萬元或以上) 40000元 新竹市 2~3年工作經驗【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=250&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 1.Perform cybersecurity incident investigation, mitigation and prevention (Security Operation Center) 2.Develop or implement the security controls to assist in detection, prevention and analysis of security threats. 3.Collect the world-wide cybersecurity intelligence (hacking activity, TTP, IOCs) and build-up the detection rules to strengthen the visibility and detection rate. 4.Perform application security enforcement and penetration-test for reducing AP vulnerability.展開 -
【2026 TSMC RDSS & AO】Quality & Reliability Engineer (Q&R)
面議(經常性薪資達4萬元或以上) 40000元 新竹縣寶山鄉 工作經歷不拘【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16577&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 品質與可靠性工程師:為守護客戶產品不受任何缺陷影響,建立優良的產品品質與可靠度,以協助客戶在市場上搶得先機、強化競爭力;QR致力於開發領先全球的電子、物理、材料與化學等科學分析專業及可靠度統計量測方法,應用於我們的產線,確保從晶片設計、製程開發、產品量產到封裝測試等階段的品質及可靠度問題皆有完整的解決方案,同時提供最先進的材料與故障分析等服務,成為公司各組織、客戶以及供應商最信任的合作夥伴。 1. Quality and Reliability roles. 2. Failure & TEM analysis, Reliability data analysis, manufacturing production quality management and reliability assessment, research, and development of new analysis protocol. 3. Customers problem resolving for production quality / reliability issues.展開 -
IT Site Reliability Engineer (SRE)
面議(經常性薪資達4萬元或以上) 40000元 新竹縣寶山鄉 3~4年工作經驗【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=5448&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. We are looking for a highly motivated and critical-thinking site reliability engineer to join tsmc. The ideal candidate should have exposure to systems in both staging and production and all technical teams. This position requires software development, support, IT operations, and on-call duties experience. Responsibilities: 1. Develop state-of-the-art applications 2. Continue to refactor existing applications 3. Transform repeatable tasks into automation tools 4. Contribute to writing tests to ensure software quality 5. Apply software design principles to ensure software quality 6. Ensure sustainability and performance of applications 7. Collaborate with peers in design and code reviews. 8. Willing to learn new IT technologies The complete interview process includes: 1. Manager interview 2. Hackerrank test 3. On-site personality and English test (which could be replaced if you have a script of officially English test 4. HR interview 5. Second manager interview (Optional assessment) 6. Technical review (Optional assessment).展開 -
A10/A14 RD Integration Engineer
面議(經常性薪資達4萬元或以上) 40000元 新竹市 工作經歷不拘【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=353&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. RD Integration starts with the definitions, including transistor architecture and design building blocks, of a new technology node. Then, a manufacturable process flow is developed for evaluations and further improvements. The tasks may involve multidiscipline technical knowledge bases and project management skills. The job will require a lot of collaborations, so frequent communication should be expected. Test structure are designed in order to evaluate the manufacturing processes. Test vehicles will be built, and real chips will be validated through yield, performance, and reliability learning cycles. The goal is to deliver an optimized semiconductor technology that will meet the required chip performance, power, area-per-function, costs, and time-to-market (PPACt) for our customers. Responsibilities: 1. Development of world-class cutting-edge technology, and responsible for the success of the A10/A14 technology: (1) Process integration across process modules, including test key design, tape out, device analysis, simulation, model, and robust. (2) Test key designs for design rule validation, electrical modeling, and yield learning. (3) Characterization of state-of-the-art devices, spice targets‘ setting for modelling, occasional bench measurement. (4) Lot handling: periodically serves as on-duty engineer to coordinate device lots‘ handling. 2. Advanced process integration development: integration and baseline sustaining to meet process KPIs on performance/ yield/ reliability/ manufacturability in A10/A14 program. 3. Advanced integration baseline process transfer to volume production. 4. Data analysis to identify the issue and issue owner. 5. Co-work with various teams to evaluate new processes and solve the issue. 6. Routine integration logistic job.展開 -
A14 R&D Device Engineer
面議(經常性薪資達4萬元或以上) 40000元 新竹市 工作經歷不拘【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=5354&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. We invite you to become an integral part of our forward-thinking team, where you will be at the vanguard of nanosheet transistor device design for our prestigious A14 technology initiative. This role offers a unique opportunity to work on the frontier of semiconductor innovation, collaborating with industry leaders and contributing to technologies that define the next generation of electronics. Responsibilities: 1. Pioneering Nanotechnology Development: (1) Seamless Integration: Integrate devices across various process modules, including the creation of test keys, execution of tape-outs, meticulous device analysis, advanced simulations, and fortification of model integrity. (2) Innovative Design: Craft precision test key designs to facilitate accurate electrical modeling and comprehensive device characterization. (3) Advanced Characterization: Define the parameters of technological progress by characterizing state-of-the-art devices, establishing SPICE modeling targets, and conducting occasional bench measurements. (4) Experimentation: Design experiments to meet device KPIs for performance and periodically serve as the on-duty engineer to coordinate device process management. 2. Diagnostic Analysis: Critical Data Assessment: Apply your analytical expertise to dissect transistor electrical and physical data, pinpointing issues and identifying responsible parties for targeted resolution. 3. Collaborative Problem-Solving: Interdisciplinary Teamwork: Join forces with a spectrum of specialized teams to scrutinize and appraise new processes, driving the resolution of complex challenges through collective insight and expertise.展開 -
A14 R&D Integration Engineer
面議(經常性薪資達4萬元或以上) 40000元 新竹市 工作經歷不拘【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=5353&source=1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Aspire to be a part of a visionary team that develops world-class, cutting-edge technology for the A14 platform? This is a call to those who wish to delve into the realm of interconnect and chip/package (2D/3D) co-optimization, where your work will be integral to our success. Responsibilities: 1. Championing Technological Excellence: (1) Optimization Wizardry: Ensure the A14 program excels by harmonizing process requirements across performance, yield, reliability, and manufacturability through strategic process integration and baseline maintenance. (2) Design & Validation Expertise: Lead the tape-out process and rigorously test key designs to validate design rules, refine electrical modeling, and elevate yield outcomes. (3) Benchmarks & Characterization: Analyze and characterize the electrical performance relative to the process, establish SPICE modeling benchmarks, and perform selective bench measurements to guarantee precision and quality. 2. Collaborative Innovation: (1) Analytical Problem-Solving: Bring your innovative mindset to team efforts, using data analysis to uncover process issues and co-developing new processes as solutions alongside talented peers. (2) Process Evolution: Play a pivotal role in evolving processes from advanced integration baselines to full-scale volume production, ensuring a smooth transition and exemplary results.展開 -
【2026 TSMC RDSS & AO】Specialty Engineer (Specialty)
面議(經常性薪資達4萬元或以上) 40000元 新竹縣寶山鄉 工作經歷不拘【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=16567&source=1111&tags=AO+2026_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 1. Novel devices developing for specialty technology. 2. Device Simulation, Test-chip design tape out and measurement system developing. 3. Process flow developing for production. 4. Collaborate with related teams for Design Collaterals (DRM/DRC/LVS/SPICE/PDK) developing.展開