轉職熱搜工作

1.臨床營養管理：住民入住72小時營養評估、體重監測、營養管理紀錄。 2.膳食管理：飲食設計、食材採購驗收、庫房管理。 3.辦理教育訓練及擔任講師。 4.跨專業團隊合作及配合機構防疫措施。 5.電腦文書基本操作。 6.專案管理及主管交辦事宜。

1、執行家電產品安規/能效測試檢驗工作，能判讀測試數據且熟悉儀器操作。 2、國內外安規報告撰寫與國內外客戶聯繫。 3、研讀相關產品之安規試驗標準、內部SOP及技術文獻。 4、協助安規文件整理判讀及實驗環境維護。 5、其他主管交辦事項。

工作項目： SSD專案 Leader，帶領團隊開發 SSD產品。 應徵條件： 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程相關科系畢業為主。 2. 具5年以上相關工作經驗： (1) 精通 SATA interface protocol. (2) 精通 PCIe interface protocol. (3) 精通 NAND flash protocol. (4) 精通 LDPC演算法。 (5) 精通 Digital design流程或具其他相關經驗者為佳。

Verification for microprocessor designs. Desired skills and experience includes: 1. Experience in processor design verification: test planning, testbench development, and documentation 2. Knowledge of assembly language, C/C++ and/or SystemVerilog 3. Knowledge of SVA or UVM methodology for block and top level verification 4. Formal property checking/formal verification methodologies 5. Proficiency in scripting languages such as Python/Perl 應徵條件： 1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。 2. 具相關工作經驗者尤佳。

工作項目： 1. 開發維護 in-house VIP 2. 支援產品線 IC 驗證計劃 工作地點：台南科學園區 應徵條件： 1. 大學、碩士以上；電機、電機與控制、資訊科學、自動控制、通訊工程、電信、資訊工程、電子、動力機械相關科系畢業為主。 2. 熟悉 SystemVerilog 驗證語言和 perl 相關 scripts。 3. 熟悉 UVM 或 VMM methodology 。 4. 熟悉 PCIE/USB/SATA 等 protocol 。 5. 具4年以上 IC 驗證相關經驗。 6. 有 VIP 開發經驗者尤佳。

• Lead GPU verification efforts across unit, subsystem, and full-chip levels, partnering closely with GPU architects, RTL design leads, performance engineers, modeling teams, and software/firmware teams. • Develop a deep understanding of GPU specifications and microarchitecture, including the 3D graphics pipeline, compute workloads, shader cores, memory hierarchy, cache/coherency, command processing, scheduling, and control subsystems. • Define the overall verification strategy, methodology, test architecture, milestones, and quality metrics for assigned GPU IPs and/or top-level GPU integration. • Drive creation and execution of comprehensive verification plans, ensuring traceability from architectural and RTL specifications through test implementation, functional coverage, assertions, and closure. • Lead development and maintenance of scalable SystemVerilog/UVM verification environments, including reusable agents, BFMs, scoreboards, reference models, checkers, and HW/SW co-simulation infrastructure. • Guide the team in developing directed, constrained-random, stress, error-injection, and scenario-based tests for graphics, compute, memory, and control features. • Drive functional and code coverage closure through rigorous coverage analysis, identification of verification gaps, and creation of targeted tests for corner cases and late-stage bug escapes. • Own regression health for the verification scope: establish regression strategy, monitor quality metrics, prioritize failures, coordinate triage, and drive root-cause resolution with design and architecture teams. • Review verification plans, testbench architecture, test code, coverage models, and debug approaches; provide technical mentorship and guidance to DV engineers. • Partner with performance, architecture, and design teams to develop performance-verification workloads, execute emulation/prototyping runs, analyze bottlenecks, and support performance, power, and area (PPA) optimization. • Drive efficient debug of complex RTL, testbench, firmware, and HW/SW co-simulation failures, clearly communicating root cause, impact, and resolution plans to cross-functional stakeholders. • Collaborate effectively across geographically distributed teams and communicate verification status, risks, and closure plans to project leadership.

1. Work on AI development for design flow 2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff flow automation

(1)MS degree or above with EE or CS background (2)1 year experience or above in IC design/verification (3)Familiar with SystemVerilog and Vera. Verilog or VHDL familiarity an advantage (4)Good knowledge on Wireless communication or architecture. (5)TCL/Perl coding experience is a plus

Key qualifications: 1. MS degree or above with EE or CS background 2. Familiar with SystemVerilog and Verilog 3. Exposure to OVM/UVM/VMM methodology 4. Exposure to constrained-random based verification environment 5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 6. Be able to develop a test bench from scratch 7. Hands on working experience on unit/block/full-chip level verification 8. Good communication skill 9. Leadership/management experience is a plus. Job descriptions: 1. Plan the verification strategy for SOC projects 2. Hands-on verification task of some of the units 3. Work closely with the design teams. 4. Drive the verification team, problem-solving on day-to-day works 5. Provide the measurable metrics for project leads and upper management. 6. Bug/coverage trend identification. Foresee the possible issues and plan for them. (MD17C0031)