轉職熱搜工作

1. Work on 7nm~3nm physical design implementation, methodology, and sign-off 2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • End-to-End DFT Leadership: Manage comprehensive DFT activities spanning architecture definition, design implementation, verification, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications • Cross-Functional Team Coordination: Lead internal DFT teams in developing and implementing robust test solutions aligned with architectural requirements • Yield Optimization Strategy: Develop comprehensive plans for diagnosability enhancement and systematic yield improvement • Location: Hsinchu, Taipei, Singapore, USA

We are looking for a highly skilled DFT CAD and Methodology Expert to develop and deploy advanced test methodologies for next-generation data center and AI ASIC. Enhancing the efficiency and quality of our ASIC development and testing procedures. The successful candidate will work within the CAD team to innovate test solutions for complex 2.5D/3DIC, ensuring high quality and yield for advanced packaging technologies. Key Responsibilities • Methodology Development: Develop and deploy robust CAD flows for scan insertion, ATPG, pattern simulation, and Memory BIST (MBIST). • Tool Automation: Create scripts (Python, TCL, Perl) to enhance and automate DFT flows, accelerating simulation runtimes and improving quality of results (QOR). • EDA Tool Integration: Collaborate with EDA vendors to enhance tools for advanced packaging, including test verification and pattern generation. • Support & Debug: Support DFT integration teams with CAD flow issues, debug complex issues, and provide technical mentorship. • 3DIC/2.5D Expertise: Develop and implement testing strategies for chiplets and TSV-based 3D stacks. • Location: Hsinchu, Taipei, Singapore.

1. 針對各類 benchmark 進行分析，辨識性能瓶頸、功耗瓶頸，並評估熱管理機制之影響。 2. 建置並實作 benchmark 之系統模型，以評估 SoC 最佳化之可行性與潛在效益。 3. 持續追蹤不同平台 benchmark 之最新進展，聚焦於系統層級之改善方向與策略。 4. 彙整分析與建模結果，提出具可落地性之系統/SoC 最佳化建議，並與跨部門團隊協作推進改善與成效驗證。

1. Develop and implement tailored DRAM controller/PHY solutions for automotive applications. Validate functionality, improve design revisions and meet performance targets as well as system requirements. 2. Perform rigorous design testing and debugging in automotive environments. Troubleshoot and propose solutions for any issues occurring in post-silicon validation. 3. System Level Cache Design & Implementation: Design and implement system level cache strategies to optimize performance and efficiency across our product range. 4. System-Level Understanding: Exhibit a system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.). 5 . Ensure that all designs comply with automotive industry standards and regulations, such as ISO 26262 and Automotive SPICE.

- 針對下一代資料中心產品，推動並導入 SoC 層級的先進功耗優化技術；與 RTL、合成與布局團隊協作，完成低功耗功能的架構規劃與導入。 - 於各設計階段（RTL → 閘級 → 佈局後）進行功耗估算與分析，提出可執行的省電建議與改善方向。 - 與 Tier-1 客戶合作制定功耗規格，並提供下一代產品的功耗估算結果與技術說明。 - 支援樣品回片後的功耗量測比對（silicon correlation）與功耗相關問題除錯（sample back / bring-up）。

1. 負責SOC內 bus 數位系統的 SystemC 平台建模與模擬，包括功能建模與性能分析。 2. 根據系統規格，建立可重複使用且具延展性的 SystemC 模型，支援系統架構規劃與驗證。 3. 參與 SoC（System-on-Chip）/IP 之行為層及高層次抽象（TLM, Transaction-Level Modeling）模型設計與驗證。 4. 與硬體、軟體和驗證團隊協同合作，協助流程整合、聯調與問題分析。 5. 撰寫技術文件與模型說明，支援團隊設計、驗證及客戶應用。

1. 研發 GNSS 基頻訊號處理算法，含 GPS、Galileo、BeiDou、GLONASS、NavIC、QZSS 和 SBAS。 2. 研發基頻硬體 C-model 和 RTL 設計驗證。 3. 研發 GNSS HW+SW receiver 於 DSP 嵌入式系統，含 SW 設計、算法實作和系統整合。

1.設計及安排說話、唱遊、舞蹈、繪畫及手工等學習活動 ，以促進幼童身心的成長 2.教導幼童良好的基本生活習慣，並保護其安全