轉職熱搜工作

1. 5G/6G通訊IP開發. 2. 多模(5G/6G)解調架構開發以及RTL coding/verification/integration.

1. Work on 2~4nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. 5G modem 架與數位電路設計 2. CLK, 測試, Reset相關設計與規劃 3. 低功耗設計 4. 系統整合 RTL 到 Gate level, 含STA

1. 規劃NPU量產測試程式 2. 測試及驗證IC功能、性能以及功耗的分析改進 3. 分析測試資料及測試相關問題，並分析良率問題並改善 4. AVS low power 的設計

We are looking for a DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality. Key Responsibilities • Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. • Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. • Perform ATPG, fault simulation, and coverage analysis. • Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. • Lead silicon bring-up and debug of test features; conduct failure and yield analysis. • Work with product teams to facilitate pattern generation, validation, and DPPM improvement.

1. 資料中心AI晶片架構設計與RTL實作 2. 資料中心SoC與AI運算平台設計與驗證 3. 系統匯流排與AI週邊設計 4. SoC系統效能分析

1. 優化數位 IC 設計流程與方法 (使用 AI) 2. 執行與管理數位 IC 設計 EDA 相關任務 (2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion (2.b) STA timing analysis 與 fixing (2.c) Netlist level QC，例如 CLP 3. 使用 AI 或 EDA 工具針對 PPA（Performance, Power, Area）進行優化 4. 將依應徵者的年資與專業經驗，提供不同的職級

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1. 參與CPU IP電路設計弱點之檢視與審查。 2. 開發 CPU IP 電路穩定度之測試項目，以排查/篩選出電路弱點。 3. 制定 CPU 電源完整性與電源量產品質方法