轉職熱搜工作

1.根據建築師或設計師之設計圖繪製施工藍圖，包含建築物內外裝修及細部構造之施工圖、建築物結構體之施工圖及水電配置圖審核 2.進行銷售面積計算、設計估價的工作 3.在建築師的指示下進行工程監督，指導施工進行 4.細部施工圖及立面磁磚計畫 5.專案時程管理、客戶變更辦理

一、使用REVIT MEP軟體，建置機電五大系統模型，機電與建築穿樑套管整合圖。 二、提出裝修尺寸與機電系統干涉疑義圖，3D轉成管路2D之ISO施工圖、料表等。 三、繪製機電施工所需相關施工圖及CSD/SEM圖面 四、孰悉使用NavisWorks、REVIT、AutoCAD等繪圖軟體 五、公共工程細部設計圖繪製/變更、預算編製、審核等專案作業 六、需具10年以上相關工作經歷

一、使用REVIT MEP軟體，建置機電五大系統模型，機電與建築穿樑套管整合圖。 二、提出裝修尺寸與機電系統干涉疑義圖，3D轉成管路2D之ISO施工圖、料表等。 三、繪製機電施工所需相關施工圖及CSD/SEM圖面 四、孰悉使用NavisWorks、REVIT、AutoCAD等繪圖軟體 五、公共工程細部設計圖繪製/變更、預算編製、審核等專案作業

1.機電工程製圖 ( 需有AutoCAD繪圖能力，SK，Bin，Revit為輔 ) 2.工程協調與問題處理、監工日報表填寫、工程施工監督管理 3.協助材料詢價與供應商收集 4.協助工程成本估算及報價 5. 其它上級交辦事項 ★有相關學歷、經歷者優先錄取，無經驗者可由公司安排培訓 ★歡迎主動積極、細心嚴謹並勇於接受挑戰，一起加入我們的行列唷！

1. 設計支援多GPU/AI Server的 AC/DC、DC/DC電源架構。 2. 與AI Server/x86硬體、製造、品質部門協作，確保設計可製造性與量產穩定性。 3. 撰寫技術文件、專利，培訓新進工程師與內部團隊。

1. 設計支援多GPU/AI Server的 AC/DC、DC/DC電源架構。 2. 與AI Server/x86硬體、製造、品質部門協作，確保設計可製造性與量產穩定性。 3. 撰寫技術文件、專利，培訓新進工程師與內部團隊。

職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).