轉職熱搜工作

職責要求 •Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted). •Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting. •Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques. •DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks. •Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization. •Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions. •Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics. •Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness. •Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists. •Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up. 任職資格 •BS/MS in Electrical/Electronics Engineering (or related). •Typically 7-10+ years of relevant experience in analog/mixed-signal IC design. •Strong fundamentals in CMOS device operation, analog design, feedback/stability, noise/jitter, and deep-submicron effects. •Proficiency with industry-standard tools (typical): Cadence Virtuoso, Spectre/ADE or HSPICE; plus modeling/scripting (e.g., Verilog-A/SystemVerilog, Python) as needed by the domain. •Ability to communicate clearly, document design decisions, and drive results in a cross-functional environment. Preferred / Nice-to-Have Experience •Experience with any high-speed interface protocols is a plus (e.g., DDR/LPDDR, HBM, UCIe, MIPI, LVDS).

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis 2. Basic knowledge of analog design 3. Mixed signal design experience is a plus. 4. SoC architecture exploration and performance analysis experience is plus. 5. Post-silicon mass production experience ((Ex: DFT, CP, FT)) is a plus. 1 . 熟悉數位IC整合流程, 包含RTL, 模擬, 時序分析, 功耗分析, 2 . 具類比IC設計的基本知識 3. 混和訊號IC設計經驗是加分項 4 . 系統架構分析經驗是加分項 5 . 具IC量產相關經驗(Ex: DFT, CP, FT)是加分項

車用電源系統，車用電子，12V or 48 V 等產品的系統電源設計/驗證之電源應用工程師，需與Designer 、PM、SW 等單位討論系統的電源設計的競爭力的分析，並驗證系統Power solution，撰寫design note 等文件，協助處理客戶開案並量產的相關系統電源問題。

1. TOP 設計包含：微架構、設計、模擬、測試 - DFT top, PAD top 2. TOP 和感測器的整合和模擬包含： - eFUSE - PVT 感測器和 aging 感測器 - 整合 IO 到晶片中並滿足客戶需求 3. 測試流程、環境和程式開發

IC 測試開發工程師 負責高速數位、類比晶片測試程式開發(AP/compu AI/ASIC/…)，產品特性異常分析與改善 新產品導入量產與生產良率測試時間優化 俱獨立帶產品作業為佳。

The candidate will design, supervise layout, help characterize transceiver front-end circuits for WiFi and Bluetooth production.

• 負責高速SerDes的開發，包括韌體設計與演算法實現、IC功能驗證、系統效能優化以及客戶支援（熟悉架構、韌體、除錯、優化及測試相關工作） • 開發自動化驗證（使用C++、Python、C#和MATLAB） • 與類比/數位團隊合作，從原型設計到量產共同開發晶片 •協助客戶設計導入並支援量產

1. Serdes IP設計開發, IC功能驗證與系統效能改善, e.g. 50G/100G/200G/300G/400G. 2. 與類比/數位/演算法團隊合作共同開發晶片從雛型設計到量產 3. 負責實作演算法或韌體設計,並在設計階段協助開發團隊建立模擬模型來增加驗證涵蓋率 4. 設計自動化驗證高速介面並除錯, 並支持IP導入產品與客戶應用

設計以資料中心和人工智慧產品為導向的高速Serdes連接PHY架構。該職位的主要職責是為世界級客戶設計並交付ASIC產品。您將參與打造低功耗、高性價比且高速的Serdes PHY設計。您將有機會拓展視野，與來自多個國家的同事合作。此職位所需的專業知識包括數位通訊設計（均衡器、有限脈衝響應濾波器）、類比設計（鎖相環、類比數位轉換器、校準）和系統單晶片（SoC）設計（微控制器、匯流排協定）。

1. Serdes/High speed interface related PHYD IP architecture planning. 2. Serdes/High speed interface related PHYD IP RTL coding. 3. Serdes/High speed interface related PHYD IP front-end and back-end integration. 4. Co-work with MAC design team and DV team for IP verification. 5. Co-work with Analog design team for PHY co-simulation.