轉職熱搜工作

Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products. • Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. • Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. • Document on new flows and processes for AMS DV. • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA

This position involves developing memory architectures, creating circuit implementation techniques and be an interface with CAD team for full verification and model generation. You have opportunity to know how memory design can be implemented into all Mediatek products.

1. Serdes PMA IP architecture planning 2. Serdes PMA IP RTL coding 3. Serdes PMA IP front-end and back-end integration 4. Co-work with PCS and MAC design team and DV team for IP verification 5. Co-work with Analog design team for PHY co-simulation 6. Co-work with Algorithm team for algorithm implementation and bit-true verification

(請留意：為加快面試安排時間，2026校招僅限定投遞5個職缺)我們在找這樣的你： 資工/資管/電子/電機/電信/通訊/電控相關研究所背景，對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣的2026年應屆畢業生。 勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。 聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration. • Document on new flows and processes for AMS Behavioral Modeling. • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc. • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA

• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 • HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。

職責要求 1. 客戶產品應用支援並提供專業的技術建議與適合的產品組合。 2. 撰寫客戶系統應用參考技術文件 3. 在客戶應用及開發上的問題，可一起co-work處理及解決能力。 4. 了解市場需求及調查，彙整最新資訊並提供給公司，讓公司針對未來市場趨勢做準備。 5. 主管交辦事項 任職資格 1.五年以上電源設計或類比IC應用研發工作經驗 2.主修電力電子，熟悉類比電路應用及電源系統研發 3.具VRM or High Power DC-DC 設計經驗 4.熟Intel VRTT或AMD SDLE測試、Battery charger、MOSFET等技術應用佳

職責要求 1. Analog Circuit Design 2. PLL/DLL、ADC/DAC、DC-DC Converter、LDO、Charge Pump IPs, etc 任職資格 1. 具備OPAmp or SAR ADC or PLL or PMIC電路設計者佳 2. 具備量產的實際經驗者佳 3. 熟悉Cadence/Synopsys EDA tool 4. 歡迎積極主動、具備責任感、喜愛創新及團隊合作的人才加入 5. 學歷 : 大學以上

Job Responsibilities • Work closely with circuit designers to complete the physical layout and its verification across different country •Receive a schematic from an Analog IC Designer and use a CAD tool to graphically design the layers of that schematic. •Use problem solving & strong communication skills, , experience, and creativity to layout circuits that meet size, schedule, and performance specifications • Run physical design verification tools to debug, improve, and verify layout blocks. • Ability to work independently & Collaborate with team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies. •Each project can last from a couple months to a year and a half. •You will likely work on just one project in that time, but may be asked to switch to something else if priorities change. • Fluent in English is a plus Job Requirement •Bachelor‘s degree in Computer Science, Electrical Engineering or related fields with 3~5 years layout experience •Including at 1~2 years in FINFET process node. 5nm/3nm is preferable •Or 5+ years experience in IC layout design, especially ≥2 years in FINFET process node. 5nm/3nm is preferable • Full-custom circuit layout/verification. Experience in one or more of the following area is preferable • Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc •Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS, etc) •Proficient at debugging/fixing LVS/DRC errors •Experience with EMIR analysis, ESD, antenna and related layout solutions •Must have strong communication skills and be a team player