轉職熱搜工作

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification.

1. 使用模擬工具分析汽車SoC的性能、功耗和熱管理指標。 2. 改進模擬模型，識別並針對SoC最佳化領域。 3. 實施策略，提升車載SoC的性能和效率。 4. 自動化評估流程，實現持續的SoC最佳化。 5. 跟進汽車SoC設計的最新進展，專注於系統層面的改進。

1.Propose design verification plan and do the execution based on IP and system HW architecture/application 2.Develop design verification environment 3.Develop required verification methodology and adopt into project

1. AI處理器, DSP, 和相對應的周邊IP驗證環境開發 2. 從module到IP的功能驗證及自動化環境 3. Formal技術探討及實作 4. 設計測試pattern以對低耗電及效能做分析 5. Post-silicon 除錯 及 耗電/效能correlation

1. Architecture design and RTL implementation of SOC platform. 2. SoC system performance analysis

1. High Speed digital design implementation 2. Integration from RTL to gate level, including flow QC, timing closure and issue analysis & solving 3. Signoff on design with mixed-signal interface 4. Design methodology and integration flow improvement

1. Familiar with HSIO spec (PCIE, USB, UFS, DP, ...etc) and system usage scenario 2. Familiar with Windows and Android OS 3. Experienced with PC south bridge design 4. Experienced with PC USB host chipset design

1. Familiar with DFT plan, methodology, implementation 2. Familiar with new DFT flow such as SSN, HSIO 3. Familar with STA, timing analysis

1. 優化相機、影音播放與編輯等多媒體架構，最大化系統效能與使用者體驗。 2. 分析 SoC 效能瓶頸並執行系統調優，提出軟硬體架構優化策略。 3. 建立 SoC 異質運算（CPU/GPU/ISP/NPU）系統模型，探索並驗證最佳化方案。 4. 提供效能分析報告，向決策團隊提出技術發展與架構演進方向。

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: * Scan chain insertion & ATPG pattern generation * Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) * Diagnosis to help manufacture process improvement 2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: * PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation * Develop & integrate DFT-related RTL design modules to test chip