轉職熱搜工作

1.熟Auto CAD 2.水電工程施工圖、竣工圖繪製相關經驗 3.負責一般文書資料處理及歸檔工作(熟Excel、Word、PowerPoint等文書軟體) 4.協助處理庶務性行政工作

※ 月薪會依學、經歷與能力調加 1. 設計圖/發包圖管理彙整。 2. 設計圖/發包圖清圖。 3. 施工圖整合檢討繪製。 4. 建築模型圖面管理。 5. 熟悉AutoCAD相關軟體，會Archicad、revit尤佳。 6. 團隊作業配合度高。 7. 需會同工務人員現場作業。 8. 變更預算整理列表。

※ 月薪會依學、經歷與能力調加 1. 設計圖/發包圖管理彙整。 2. 設計圖/發包圖清圖。 3. 施工圖整合檢討繪製。 4. 建築模型圖面管理。 5. 熟悉AutoCAD相關軟體，會Archicad、revit尤佳。 6. 團隊作業配合度高。 7. 需會同工務人員現場作業。 8. 變更預算整理列表。

1負販賣部商品包裝、整備、管理。 2.社交平台管理(內更新、訊息. 等)。 3.公司文宣及圖片修改編輯(需要會簡易的美 編軟體) 4.維護環境整潔及配合公司調度工作支援。 5.教導客人DIY手作商品。 6.解說三星蔥生長環境.種植.施肥.採收的方 式。 7.外場下田導覽解說

• Lead FPGA development activities across functional prototyping, emulation, performance evaluation, and database generation flows. • Work closely with architecture, design, verification, software, firmware, and performance teams to understand system requirements and define FPGA implementation strategy. • Drive FPGA functional flow, including RTL integration, FPGA partitioning, synthesis, place-and-route, timing constraints, timing closure, bitstream generation, bring-up, and debug. • Drive FPGA performance flow to support in-house performance evaluation, workload execution, data collection, profiling, and performance database generation. • Design, implement, integrate, and optimize FPGA logic using Verilog/SystemVerilog/VHDL. • Develop and maintain FPGA prototypes and emulation platforms for system validation, software enablement, firmware development, and hardware/software debug. • Support performance analysis by enabling representative workloads, collecting runtime metrics, identifying bottlenecks, and collaborating with architecture/design teams on improvement opportunities. • Define and improve FPGA methodology, automation, build flows, regression infrastructure, and debug processes for both functional and performance use cases. • Support and integrate interfaces such as PCIe, DDR, AXI, Ethernet, SPI, I2C, UART, and other standard protocols. • Provide technical leadership, mentor engineers, coordinate cross-functional execution, and drive issue resolution across multi-site teams.

1.RTL platform design integration (clock/reset/power/bus design and architecture, MBIST, etc.) - use for FPGA and Emulator should also be considered 2.Integration quality check (RTL/SDC/Power spec signoff check)

Senior Technical Program Leader | USB3/USB4 Customer Issue Resolution

•重點開發技術: 系統開發、高速資料實體層(physical layer) 資料傳輸軟體開發、優化硬體效能及產品量產品質控管 •主要目標: 完成Enterprise/AI/xPU等相關產業客製化IC的軟韌體開發與系統整合，並協助客戶產品量產，有SLT的經驗 •負責新產品的系統設計與開發，確保符合公司及客戶的需求 •協助量產過程中的技術問題解決，並提供專業建議以提升生產效率與品質 •與跨部門團隊合作，確保產品從設計到量產的順利過渡 •分析並改善現有系統和流程，以提高產品質量和生產效率 •參與產品測試和驗證，確保產品符合相關標準和規範

• Lead GPU verification efforts across unit, subsystem, and full-chip levels, partnering closely with GPU architects, RTL design leads, performance engineers, modeling teams, and software/firmware teams. • Develop a deep understanding of GPU specifications and microarchitecture, including the 3D graphics pipeline, compute workloads, shader cores, memory hierarchy, cache/coherency, command processing, scheduling, and control subsystems. • Define the overall verification strategy, methodology, test architecture, milestones, and quality metrics for assigned GPU IPs and/or top-level GPU integration. • Drive creation and execution of comprehensive verification plans, ensuring traceability from architectural and RTL specifications through test implementation, functional coverage, assertions, and closure. • Lead development and maintenance of scalable SystemVerilog/UVM verification environments, including reusable agents, BFMs, scoreboards, reference models, checkers, and HW/SW co-simulation infrastructure. • Guide the team in developing directed, constrained-random, stress, error-injection, and scenario-based tests for graphics, compute, memory, and control features. • Drive functional and code coverage closure through rigorous coverage analysis, identification of verification gaps, and creation of targeted tests for corner cases and late-stage bug escapes. • Own regression health for the verification scope: establish regression strategy, monitor quality metrics, prioritize failures, coordinate triage, and drive root-cause resolution with design and architecture teams. • Review verification plans, testbench architecture, test code, coverage models, and debug approaches; provide technical mentorship and guidance to DV engineers. • Partner with performance, architecture, and design teams to develop performance-verification workloads, execute emulation/prototyping runs, analyze bottlenecks, and support performance, power, and area (PPA) optimization. • Drive efficient debug of complex RTL, testbench, firmware, and HW/SW co-simulation failures, clearly communicating root cause, impact, and resolution plans to cross-functional stakeholders. • Collaborate effectively across geographically distributed teams and communicate verification status, risks, and closure plans to project leadership.