轉職熱搜工作

工作項目： Verification for High Speed PHY projects, which includes: 1. Responsibility for test plans, testbench documentation and implementation. 2. Use SystemVerilog language, SVA and UVM methodology for block level verification. 3. Debug tests with design engineers to deliver functionally correct design blocks. 4. Close coverage measures to identify verification holes and show progress towards tape-out. 5. Write scripts to automate routine parts of verification workflow. 應徵條件： 1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。 2. 具0~3年下列經驗之一者尤佳： (1) Experience verifying digital logic at RTL using SystemVerilog for FPGAs and/or ASICs. (2) Experience verifying digital systems using standard IP components/interconnects. (3) Experience creating and using verification components and environments in standard verification methodology. 3. Preferred qualifications: (1) Experience with high speed MAC/PHY RTL design or verification. (2) Experience with UVM methodology and coding. (3) Good English verbal communication skills.

工作項目： 1. High-Performance CPU/GPU Timing & Power Integrity Signoff 2. High-Performance CPU/GPU Post-Silicon Validation & Debug, Sim-to-Silicon Correlation 3. 協同開發 CPU/GPU Advanced DFT, On-Chip PVT Sensor, Performance Improvement & Power Management 等先進技術 4. 支援產品 SoC Projects，協同執行 High-Performance CPU/GPU 專案開發，導入先進 IP 及技術 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 SoC Integration & Design Flow、Frontend/Backend/DFT/Timing/IR Drop/Power Analysis EDA Tools。 3. 有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 4. 有 Chip-Level, Package & PCB Power Integrity Optimization 經驗尤佳。 5. 有On-Chip PVT Sensor 開發經驗尤佳。 6. 有Post-Silicon Validation, Debug 及 RMA 分析經驗尤佳。 7. 積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 1. SOC integrator! A challenging job for integrating the designs from over 100 digital designers and tens of analog designers. A challenging job of using deep submicron process. 2. Building & Improving the standard environment for digital designers to run front-end flow, such as synthesis, STA analysis, linting, and so on. 3. Cooperating with APR designers for backend timing closure. 4. Block / Whole-Chip CTS (Clock-tree Synthesis) analysis and improvement. 應徵條件： 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程等相關科系畢業為主。 2. 熟悉 verilog, verdi, STA, synthesis. 3. 具 CTS(Clock tree synthesis) Design/Debug經驗者尤佳。 4. 會寫 script如 perl者更佳。 5. 具六年以上相關工作經驗。

工作項目： 1. 開發維護 in-house VIP 2. 支援產品線 IC 驗證計劃 工作地點：台南科學園區 應徵條件： 1. 大學、碩士以上；電機、電機與控制、資訊科學、自動控制、通訊工程、電信、資訊工程、電子、動力機械相關科系畢業為主。 2. 熟悉 SystemVerilog 驗證語言和 perl 相關 scripts。 3. 熟悉 UVM 或 VMM methodology 。 4. 熟悉 PCIE/USB/SATA 等 protocol 。 5. 具4年以上 IC 驗證相關經驗。 6. 有 VIP 開發經驗者尤佳。

1. Summary Realtek Semiconductor Corp., located in the Hsinchu Science-based Industrial Park, Taiwan‘s 〝Silicon Valley〝, established in 1987. Realtek‘s efforts to provide the ultimate in pioneering IC technology — along with its firm commitment to creating unique and innovative designs for a broad range of high-tech applications — have won the company a worldwide reputation and made possible a favorable and consistent growth rate in the years since its establishment. In line with the Realtek culture of 〝Self-confidence and trust in people〝, we believe that we can achieve our best, and trust our colleagues can also do the same. Working and learning in Realtek, we openly share knowledge and experience with one another to inspire innovation and pursue growth of the company, as well the individuals. Talent is the important capital of Realtek. Welcome to Join Realtek Family! 2. Essential Job Functions ‧Locate in Southern part of Germany (Frankfurt to Stuttgart, or Stuttgart to Munich) ‧Provide pre-sales and post-sales support. ‧Understand customer requirements, and deliver technical presentations, reports, documents and technology demonstrations. ‧Support customer product development and design. ‧Support customer issue analysis and resolve. ‧On-site support for debug or certification test. ‧Cross-functional collaboration with Realtek internal resources. 3. Education, Skills, Abilities, And Experience Required ‧M.S. or B.S. in Engineering or equivalent. ‧3 to 5 years of progressive professional technical experience in IC design or related areas, direct experience in IC design house FAE is preferred. ‧Strong analytical and problem solving skills. ‧Strong written/verbal communication and negotiation skills. ‧Being proactive and willing to take initiatives. ‧Ability to work independently to achieve goals. ‧Ability to understand and explain technical issues and solutions to technical and non-technical personnel. ‧Native German skill. ‧Medium or higher English skill. ‧Familiar with Ethernet protocols will be a plus. ‧Familiar with Automotive ecosystem will be a plus. ‧Basic or higher Chinese skill will be a plus. ‧Experience of Linux system will be a plus. 4. Industry Automotive Ethernet, Semiconductor 5. Employment Type Full-time 6. Job Functions Engineering, Business Development

工作項目： 1. Software and utility development for ARM Architecture based Complex CPU Subsystem Platform 2. CPU function validation and testing software development 3. CPU post-silicon issue analysis, debug & resolving 應徵條件： 1. 碩士以上; 資訊工程、資訊科學、電機工程、電子工程等相關科系畢業。 2. 熟悉 ARMv7/v8/v9-A CPU 架構，有 ARM Cortex-A CPU system software 經驗尤佳。 3. 熟悉以下經驗者： (a) CPU 之系統程式或工具開發。 (b) CPU/OS之 debug 及問題分析。 (c) CPU post-silicon issue analysis, debug & resolving。 (d) 具備 Verilog RTL 及相關工具軟體開發經驗。 4. 積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU Technology 有興趣者。

Verification for microprocessor designs. Desired skills and experience includes: 1. Experience in processor design verification: test planning, testbench development, and documentation 2. Knowledge of assembly language, C/C++ and/or SystemVerilog 3. Knowledge of SVA or UVM methodology for block and top level verification 4. Formal property checking/formal verification methodologies 5. Proficiency in scripting languages such as Python/Perl

工作項目： Verification for High Speed PHY projects, which includes: 1. Responsibility for test plans, testbench documentation and implementation. 2. Use SystemVerilog language, SVA and UVM methodology for block level verification. 3. Debug tests with design engineers to deliver functionally correct design blocks. 4. Close coverage measures to identify verification holes and show progress towards tape-out. 5. Write scripts to automate routine parts of verification workflow.

職務說明： 1. Create formal verification test plan. 2. Develop formal verification environment. 3. Run formal verification and regression, debug failures and analyze coverage. 4. Support other members in deploying formal verification. 5. Survey new formal applications and develop related workflow. 6. Enhance and maintain formal verification workflow. 徵才條件： A. Key qualifications : 1. Master‘s or above in Electrical Engineering, Computer Science. 2. Familiar with standard verification concepts and workflow. 3. Familiar with SystemVerilog and Verilog. 4. Familiar with scripting languages (Perl, Python, etc.). 5. Good communication skills. B. Preferred qualifications : 1. Familiar with SystemVerilog Assertion (SVA). 2. Familiar with formal verification methodology. 3. Familiar with formal tools (JasperGold, VCFormal). 4. Practical experience in formal verification, able to apply strategies to resolve issues during the verification process. 5. Familiar with bus protocol concept (AMBA). 6. Familiar with UVM methodology.

工作內容： 開發生醫感測器及周邊類比電路 徵才條件： 1. 碩士以上，具低雜訊低功耗類比電路設計經驗 2. 有SDM電路經驗尤佳