轉職熱搜工作

1. SoC IC implementation 規劃設計 2. DFT 規劃設計 以及timing closure signoff 3. 設計方法流程開發及優化 4. 工作地點:新竹/台北

1. 使用模擬工具分析汽車SoC的性能、功耗和熱管理指標。 2. 改進模擬模型，識別並針對SoC最佳化領域。 3. 實施策略，提升車載SoC的性能和效率。 4. 自動化評估流程，實現持續的SoC最佳化。 5. 跟進汽車SoC設計的最新進展，專注於系統層面的改進。

1. Develop systematic algorithms to alleviate design challenges, including implementation, process what-if assessment, system performance evaluation, in advanced nodes or package 2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies 3. Explore new EDA features and define improvement direction from MTK product requirements

1. Perform pre-silicon and post-silicon correlation and modeling related to adaptive voltage scaling and on-die sensor 2. Develop and improve post-silicon testing methodologies related to adaptive voltage scaling and on-die sensor

1. CPU功耗分析 (設計 vs. 量測), 確保CPU功耗體質 2. CPU最大電流分析 (設計 vs. 量測), 驗證過電流保護機制確保系統穩定性 3. PMIC+PDN+CPU 功耗效率優化 1. CPU power pre-silicon vs. post-silicon correlation. Ensure CPU power quality 2. CPU max. current pre-silicon vs. post-silicon correlation. Validate max. current protection technique for system stability 3. PMIC+PDN+CPU power efficient optimization

1. HSI IP development 2. Short term: Help integration of on-going project including QC. 3. Long term: Deep learn into 3rd party HSI IP. Know the detailed spec of PCIe/UCIE/USB4 and able to co-work with DV.

1. Develop 3.5D methodology from RTL to GDS and Package 2. Coordinate Thermal and PI/SI team to deal with high power design 3. Execute the project at different phases

1. AI處理器, DSP, 和相對應的周邊IP驗證環境開發 2. 從module到IP的功能驗證及自動化環境 3. Formal技術探討及實作 4. 設計測試pattern以對低耗電及效能做分析 5. Post-silicon 除錯 及 耗電/效能correlation

1. Design and RTL implementation of SoC debug modules 2. Integration and verification of debug components (e.g., trace, monitor, access port) 3. Debug signal capture, trace, and analysis for SoC platforms 4. Support SoC debug flow and issue localization 5. Collaborate with cross-functional teams to optimize debug performance 6. Documentation and test specification for SoC debug features 7. Location: Taipei/Hsinchu