轉職熱搜工作

1. 對專利相關知識有所了解及能與RD人員進行提案技術內容進行討論。 2. 具有研發相關背景先不限機構、電子或其他領域。 3. 針對IP部門檢索報告內容，能進行分析其主要技術特徵及評估並能與IP討論進行設計迴避的方向。 4. 對於電腦周邊的專利佈局及策略能有初步概念及提供主管相關建議資料。

※ 年度獎金原則為2個月，九成同仁2個月以上。 ※ 月薪依學、經歷與能力調加。 1. 實驗規劃與實作。 2. 依照訂單進行機構繪圖(繪圖、拆圖、建BOM)。 3. 蒐集產線問題並分析、規劃、執行解決方案。 4. 視表現及能力評估參與各項研發專案。

工作項目： Memory Compiler quality verification and support。 應徵條件： 1. 碩士以上; 電機、電子、資工相關科系畢業為主。 2. Familiar with front-end & back-end model including verilog, liberty (nldm/ccs/lvf), dft, redhawk, lef, spice view。 3. Familiar with physical verification flows including drc, erc, lvs, rc extraction。 4. Familiar with Hspice, Spectre, Solido simulation tool & Virtuso, Laker layout tool。 5. Familiar with Scripting language: Python/Verilog/TCL/Shell/Makefile/C。 6. 具以下條件者佳： (1) 熟悉SRAM操作原理及bit cell特性。 (2) 從事SRAM錯誤分析及良率改善。 (3) 具矽智財合約管理經驗。

Qualifications • Associate or Bachelor‘s degree in Electrical Engineering, Automation, Control Systems, or related field • 1–3 years of experience in SCADA / DCS system development or maintenance • Basic English reading ability for technical documentation • Understanding of SCADA / DCS system architecture • Experience analytical and troubleshooting skills • Experience with Emerson DeltaV system Responsibilities • Design and develop SCADA graphical interfaces • Configure, maintain, and optimize Emerson DeltaV systems • Create and maintain SCADA graphics and data points • Integrate and test SCADA with PLC systems • Support system commissioning and on-site testing • Perform system troubleshooting and optimization • Prepare technical documentation and operation manuals

工作經驗：3年以上 工作項目： 1. Standard Cell Library 支援與維護。 2. NVM (eFuse, OTP, eFlash) IP 支援與維護。 應徵條件： 1. 碩士及以上電機、資訊相關科系畢業。 2. 熟悉 Verilog語法與RTL Synthesis及Simulation 等相關數位IC Design Flow者佳。 3. 有Standard Cell Library、Memory Compiler及 NVM相關經驗者佳。 4. 有矽智財管理或合約管理相關經驗者佳。

• Working with design, and architecture teams to define power targets. • Identifying opportunities for power optimization in existing design, and new power saving features, • Defining power optimization solutions.

1. 使用 VHDL/Verilog 進行 CPLD 電路邏輯開發。 2. 執行模擬、合成與晶片燒錄，並進行 Debug。 3. 設計 I²C、SPI、UART 等數位介面，與硬體電路整合。 4. 確保設計符合時序需求，並優化資源與功耗。 5. 產出設計規格書/測試報告，並與韌體、製造團隊協同作業。

1. Work with analog design team for USB/PCIE/SATA quality 2. Responsible for front-end design IP verification and debugging. 3. projects coordination and management.

1. Baseband Hardware Design & Schematic Capture Design and own baseband circuits, including schematic capture, component selection, BOM maintenance, and multi-layer PCB stack-up definition. 2. PCB Layout Review & Design Guidance Guide layout engineers and perform detailed layout reviews to meet high-speed signal integrity (SI), power delivery network (PDN), and impedance control requirements. 3. Power Consumption & PDN Performance Tuning Conduct power domain analysis, power rail ripple measurement, and PDN/LDO optimization to improve overall system power consumption and stability. 4. System Integration, Board Bring-up & Debugging Execute board bring-up, baseband signal verification, and system-level performance testing; perform root-cause analysis for hardware bugs and drive technical issues to resolution. 5. Certification & Manufacturing Support Assist with regulatory/compliance certifications (e.g., FCC/CE) and support NPI (New Product Introduction) and mass production line issues.