轉職熱搜工作

1. CPU system design and performance analysis 2. AMBA System bus architecture and integration 3. IP and system design and verification

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis 2. Basic knowledge of analog design 3. Mixed signal design experience is a plus. 4. SoC architecture exploration and performance analysis experience is plus. 5. Post-silicon mass production experience ((Ex: DFT, CP, FT)) is a plus. 1 . 熟悉數位IC整合流程, 包含RTL, 模擬, 時序分析, 功耗分析, 2 . 具類比IC設計的基本知識 3. 混和訊號IC設計經驗是加分項 4 . 系統架構分析經驗是加分項 5 . 具IC量產相關經驗(Ex: DFT, CP, FT)是加分項

- 負責資料中心相關 IP 整合，涵蓋從合成、DFT 至 GDS 交付完整流程 - 負責先進製程晶片整合，涵蓋從synthesis QC Sign-off & Tapeout

Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.

1. Make test pattern plan to cover system bring-up for MP (CP/FT, system test, DVT, HQA, correlation, DPPM reduction) 2. Debug post-silicon issue to identify design weakness and solution finding 3. Correct post-silcion measurement vs. pre-silicon simulaiton, including process, performance, power.

- Optimize GPU performance, area/power for representative workloads (graphics and compute) from the perspectives of memory sub-system, low-power design/policy and implementation strategy. - System modeling framework to simulate hardware with different accuracy/throughput tradeoffs at different stages of the design; supervise Performance/Power/Area investigation/validation and facilitate architecture/design decisions

- Collaborate with architects and cross-functional teams to understand GPU specs and define verification strategies. - Develop SystemVerilog/UVM test frameworks and co-simulation environments; verify GPU logic at unit, subsystem, and top levels. - Create and execute verification test plans, focusing on functional coverage. - Generate random and directed test sequences; maintain testbench, scoreboard, BFMs, and regression. - Perform RTL and coverage analysis; optimize test scenarios and address bug escapes. - Support performance verification, emulation, data collection, debugging, and PPA improvements. - Conduct formal verification.

1.軟體規劃製作。 2.自動控制產品規劃、設計、監控。 3.電氣工程系統規劃、設計、監控，程式設計。 4.負責自動化設備、系統介面之維護及改善。 5.負責自動化系統各類規範與相關文件之撰寫、修改。

此職缺為數位IC設計工程師，專注於 Camera / ISP 解決方案。您將負責為多元產品（如智慧型手機、平板、車用系統及家庭娛樂設備）設計具產業競爭力的影像訊號處理器（ISP）。 工作內容： - 與 ISP 演算法工程師密切合作，設計具競爭力的 ISP / CV 硬體架構 - 交付在高效能、低功耗、最小面積之間達到最佳平衡的硬體解決方案 - 負責 RTL 設計、模擬、驗證、合成以及系統整合 - 具備創新能力，能進行 IP 設計之微架構制定與系統架構討論 - 具良好的跨部門合作、問題解決能力與技術溝通能力

1. 數位 IC 設計（RTL/電路合成/整合/驗證） 2. SoC 層級晶片設計/整合 3. DFT 相關設計/規劃/整合 4. 靜態時序分析以及收斂 5. 設計流程開發與最佳化 6. 工作地點：台北/新竹